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Commit 032405a7 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter',... 

Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next

* clk-imx6-ocram:
  :  - i.MX6SX ocram_s clk support
  clk: imx: add ocram_s clock for i.mx6sx

* clk-missing-put:
  :  - Add missing of_node_put()s in some i.MX clk drivers
  clk: imx6sll: fix missing of_node_put()
  clk: imx6ul: fix missing of_node_put()

* clk-tegra-sdmmc-jitter:
  :  - Tegra SDMMC clk jitter improvements with high speed signaling modes
  clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
  clk: tegra: Add sdmmc mux divider clock
  clk: tegra: Refactor fractional divider calculation
  clk: tegra: Fix includes required by fence_udelay()

* clk-allwinner:
  clk: sunxi-ng: add A64 compatible string
  dt-bindings: add compatible string for the A64 DE2 CCU
  clk: sunxi-ng: r40: Export video PLLs
  clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
  clk: sunxi-ng: r40: Add minimal rate for video PLLs

* clk-uniphier:
  :  - Uniphier NAND, USB3 PHY, and SPI clk support
  clk: uniphier: add clock frequency support for SPI
  clk: uniphier: add more USB3 PHY clocks
  clk: uniphier: add NAND 200MHz clock
parents 4a18ef5b d7b7c00d 7f5eac59 c76a69e4 cec5dfa4 ff388ee3

Documentation/devicetree/bindings/clock/sun8i-de2.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Required properties : 
		- "allwinner,sun8i-a83t-de2-clk"

		- "allwinner,sun8i-h3-de2-clk"

		- "allwinner,sun8i-v3s-de2-clk"

		- "allwinner,sun50i-a64-de2-clk"

		- "allwinner,sun50i-h5-de2-clk"



- reg: Must contain the registers base address and length

drivers/clk/imx/clk-imx6sll.c

+1 −0
Original line number Diff line number Diff line
@@ -92,6 +92,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node) 


	np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");

	base = of_iomap(np, 0);

	of_node_put(np);

	WARN_ON(!base);



	/* Do not bypass PLLs initially */

drivers/clk/imx/clk-imx6sx.c

+1 −0
Original line number Diff line number Diff line
@@ -402,6 +402,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) 
	clks[IMX6SX_CLK_GPT_BUS]      = imx_clk_gate2("gpt_bus",       "perclk",            base + 0x6c, 20);

	clks[IMX6SX_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",    "perclk",            base + 0x6c, 22);

	clks[IMX6SX_CLK_GPU]          = imx_clk_gate2("gpu",           "gpu_core_podf",     base + 0x6c, 26);

	clks[IMX6SX_CLK_OCRAM_S]      = imx_clk_gate2("ocram_s",       "ahb",               base + 0x6c, 28);

	clks[IMX6SX_CLK_CANFD]        = imx_clk_gate2("canfd",         "can_podf",          base + 0x6c, 30);



	/* CCGR2 */

drivers/clk/imx/clk-imx6ul.c

+1 −0
Original line number Diff line number Diff line
@@ -135,6 +135,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 


	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");

	base = of_iomap(np, 0);

	of_node_put(np);

	WARN_ON(!base);



	clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));

drivers/clk/sunxi-ng/ccu-sun8i-de2.c

+4 −7
Original line number Diff line number Diff line
@@ -288,17 +288,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { 
		.compatible = "allwinner,sun8i-v3s-de2-clk",

		.data = &sun8i_v3s_de2_clk_desc,

	},

	{

		.compatible = "allwinner,sun50i-a64-de2-clk",

		.data = &sun50i_a64_de2_clk_desc,

	},

	{

		.compatible = "allwinner,sun50i-h5-de2-clk",

		.data = &sun50i_a64_de2_clk_desc,

	},

	/*

	 * The Allwinner A64 SoC needs some bit to be poke in syscon to make

	 * DE2 really working.

	 * So there's currently no A64 compatible here.

	 * H5 shares the same reset line with A64, so here H5 is using the

	 * clock description of A64.

	 */

	{ }

};