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Commit cec5dfa4 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.19' of... 

Merge tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes for 4.19 from Maxime Ripard:

Our usual bunch of clock patches, this time to enable the A64 display
engine clocks controller mostly.

* tag 'sunxi-clk-for-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: add A64 compatible string
  dt-bindings: add compatible string for the A64 DE2 CCU
  clk: sunxi-ng: r40: Export video PLLs
  clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
  clk: sunxi-ng: r40: Add minimal rate for video PLLs
parents ce397d21 01951563

Documentation/devicetree/bindings/clock/sun8i-de2.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Required properties : 
		- "allwinner,sun8i-a83t-de2-clk"

		- "allwinner,sun8i-h3-de2-clk"

		- "allwinner,sun8i-v3s-de2-clk"

		- "allwinner,sun50i-a64-de2-clk"

		- "allwinner,sun50i-h5-de2-clk"



- reg: Must contain the registers base address and length

drivers/clk/sunxi-ng/ccu-sun8i-de2.c

+4 −7
Original line number Diff line number Diff line
@@ -288,17 +288,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { 
		.compatible = "allwinner,sun8i-v3s-de2-clk",

		.data = &sun8i_v3s_de2_clk_desc,

	},

	{

		.compatible = "allwinner,sun50i-a64-de2-clk",

		.data = &sun50i_a64_de2_clk_desc,

	},

	{

		.compatible = "allwinner,sun50i-h5-de2-clk",

		.data = &sun50i_a64_de2_clk_desc,

	},

	/*

	 * The Allwinner A64 SoC needs some bit to be poke in syscon to make

	 * DE2 really working.

	 * So there's currently no A64 compatible here.

	 * H5 shares the same reset line with A64, so here H5 is using the

	 * clock description of A64.

	 */

	{ }

};

drivers/clk/sunxi-ng/ccu-sun8i-r40.c

+32 −26
Original line number Diff line number Diff line
@@ -66,8 +66,9 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 
				   CLK_SET_RATE_UNGATE);



/* TODO: The result of N/M is required to be in [8, 25] range. */

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",

					    "osc24M", 0x0010,

					    192000000,	/* Minimum rate */

					    8, 7,	/* N */

					    0, 4,	/* M */

					    BIT(24),	/* frac enable */
@@ -152,8 +153,9 @@ static struct ccu_nk pll_periph1_clk = { 
};



/* TODO: The result of N/M is required to be in [8, 25] range. */

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",

static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",

					    "osc24M", 0x030,

					    192000000,	/* Minimum rate */

					    8, 7,	/* N */

					    0, 4,	/* M */

					    BIT(24),	/* frac enable */
@@ -654,7 +656,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 


static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };

static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,

				 0x104, 0, 4, 24, 3, BIT(31), 0);

				 0x104, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,

				 0x108, 0, 4, 24, 3, BIT(31), 0);
@@ -666,9 +669,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents, 
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,

			       0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,

				 0x118, 0, 4, 24, 3, BIT(31), 0);

				 0x118, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,

				 0x11c, 0, 4, 24, 3, BIT(31), 0);

				 0x11c, 0, 4, 24, 3, BIT(31),

				 CLK_SET_RATE_PARENT);



static const char * const deinterlace_parents[] = { "pll-periph0",

						    "pll-periph1" };
@@ -698,7 +703,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 


static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };

static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,

				 0x150, 0, 4, 24, 2, BIT(31), 0);

				 0x150, 0, 4, 24, 2, BIT(31),

				 CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(hdmi_slow_clk,	"hdmi-slow",	"osc24M",

		      0x154, BIT(31), 0);

drivers/clk/sunxi-ng/ccu-sun8i-r40.h

+6 −2
Original line number Diff line number Diff line
@@ -25,7 +25,9 @@ 
#define CLK_PLL_AUDIO_2X	4

#define CLK_PLL_AUDIO_4X	5

#define CLK_PLL_AUDIO_8X	6

#define CLK_PLL_VIDEO0		7



/* PLL_VIDEO0 is exported */



#define CLK_PLL_VIDEO0_2X	8

#define CLK_PLL_VE		9

#define CLK_PLL_DDR0		10
@@ -34,7 +36,9 @@ 
#define CLK_PLL_PERIPH0_2X	13

#define CLK_PLL_PERIPH1		14

#define CLK_PLL_PERIPH1_2X	15

#define CLK_PLL_VIDEO1		16



/* PLL_VIDEO1 is exported */



#define CLK_PLL_VIDEO1_2X	17

#define CLK_PLL_SATA		18

#define CLK_PLL_SATA_OUT	19

include/dt-bindings/clock/sun8i-r40-ccu.h

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,10 @@ 
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_

#define _DT_BINDINGS_CLK_SUN8I_R40_H_



#define CLK_PLL_VIDEO0		7



#define CLK_PLL_VIDEO1		16



#define CLK_CPU			24



#define CLK_BUS_MIPI_DSI	29