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Commit ff388ee3 authored by Kunihiko Hayashi's avatar Kunihiko Hayashi Committed by Stephen Boyd
Browse files

clk: uniphier: add clock frequency support for SPI 



Add clock control for SPI controller on UniPhier SoCs.

Signed-off-by: default avatarKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9d222574

drivers/clk/uniphier/clk-uniphier-peri.c

+9 −0
Original line number Diff line number Diff line
@@ -27,6 +27,12 @@ 
#define UNIPHIER_PERI_CLK_FI2C(idx, ch)					\

	UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))



#define UNIPHIER_PERI_CLK_SCSSI(idx)					\

	UNIPHIER_CLK_GATE("scssi", (idx), "spi", 0x20, 17)



#define UNIPHIER_PERI_CLK_MCSSI(idx)					\

	UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)



const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {

	UNIPHIER_PERI_CLK_UART(0, 0),

	UNIPHIER_PERI_CLK_UART(1, 1),
@@ -38,6 +44,7 @@ const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = { 
	UNIPHIER_PERI_CLK_I2C(6, 2),

	UNIPHIER_PERI_CLK_I2C(7, 3),

	UNIPHIER_PERI_CLK_I2C(8, 4),

	UNIPHIER_PERI_CLK_SCSSI(11),

	{ /* sentinel */ }

};
@@ -53,5 +60,7 @@ const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = { 
	UNIPHIER_PERI_CLK_FI2C(8, 4),

	UNIPHIER_PERI_CLK_FI2C(9, 5),

	UNIPHIER_PERI_CLK_FI2C(10, 6),

	UNIPHIER_PERI_CLK_SCSSI(11),

	UNIPHIER_PERI_CLK_MCSSI(12),

	{ /* sentinel */ }

};

drivers/clk/uniphier/clk-uniphier-sys.c

+8 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512),	/* 270 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),

	UNIPHIER_LD4_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_LD4_SYS_CLK_SD,
@@ -111,6 +112,7 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1),		/* 250 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),

	UNIPHIER_CLK_FACTOR("spi", 1, "spll", 1, 32),

	UNIPHIER_LD4_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_LD4_SYS_CLK_SD,
@@ -137,6 +139,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25),	/* 270 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 32),

	UNIPHIER_LD4_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_LD4_SYS_CLK_SD,
@@ -151,6 +154,7 @@ const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125),	/* 2949.12 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),

	UNIPHIER_PRO5_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_PRO5_SYS_CLK_SD,
@@ -167,6 +171,7 @@ const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 96, 1),		/* 2400 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 48),

	UNIPHIER_PRO5_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_PRO5_SYS_CLK_SD,
@@ -193,6 +198,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("vspll", -1, "ref", 80, 1),		/* 2000 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),

	UNIPHIER_LD11_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_LD11_SYS_CLK_EMMC(4),
@@ -227,6 +233,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("vppll", -1, "ref", 504, 5),	/* 2520 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),

	UNIPHIER_LD11_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),

	UNIPHIER_LD11_SYS_CLK_EMMC(4),
@@ -271,6 +278,7 @@ const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[] = { 
	UNIPHIER_CLK_FACTOR("s2pll", -1, "ref", 88, 1),		/* IPP: 2400 MHz */

	UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),

	UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 40),

	UNIPHIER_CLK_FACTOR("spi", -1, "spll", 1, 40),

	UNIPHIER_LD20_SYS_CLK_SD,

	UNIPHIER_LD11_SYS_CLK_NAND(2),

	UNIPHIER_SYS_CLK_NAND_4X(3),