clk: msm: clock-cpu-titanium: Enable HF PLL early stage of boot

At the early_initcall before we switch APSS RCG to source from APSS PLL,
make sure that the PLL is enabled. The boolean flags test_ctl_dbg and
init_test_ctl added to control the test bits of PLL.

Change-Id: I2189d72414de7fcce31e2686d7ba476928c5fa80
Signed-off-by: Taniya Das <tdas@codeaurora.org>