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Commit 0e71a6df authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: msm: clock-pll: Add test_ctl_dbg flag to configure test bits 



The PLL hardware configuration does not mandate to modify the test control
bits of the PLL, in those cases introduce a flag which when present will
skip configuration of the test control bits.

Change-Id: I70588398cffae193d56cb510faa19b1f96f05fea
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 566d1d5d

drivers/clk/msm/clock-pll.c

+11 −9
Original line number Diff line number Diff line
@@ -338,6 +338,7 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
		writel_relaxed(pll->vals.test_ctl_lo_val,

				PLL_TEST_CTL_LO_REG(pll));



	if (!pll->test_ctl_dbg) {

		/* Enable test_ctl debug */

		mode |= BIT(3);

		writel_relaxed(mode, PLL_MODE_REG(pll));
@@ -348,6 +349,7 @@ static int variable_rate_pll_clk_enable(struct clk *c) 
		writel_relaxed(testlo, PLL_TEST_CTL_LO_REG(pll));

		/* Wait for the write to complete */

		mb();

	}



	/* Disable PLL bypass mode. */

	mode |= PLL_BYPASSNL;

include/soc/qcom/clock-pll.h

+2 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) 
 * @status_reg: status register, contains the lock detection bit

 * @init_test_ctl: initialize the test control register

 * @pgm_test_ctl_enable: program the test_ctl register in the enable sequence

 * @test_ctl_dbg: if false will configure the test control registers.

 * @masks: masks used for settings in config_reg

 * @vals: configuration values to be written to PLL registers

 * @freq_tbl: pll freq table
@@ -151,6 +152,7 @@ struct pll_clk { 


	bool init_test_ctl;

	bool pgm_test_ctl_enable;

	bool test_ctl_dbg;



	struct pll_config_masks masks;

	struct pll_config_vals vals;