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Commit d5c2948f authored by Taniya Das's avatar Taniya Das Committed by Gerrit - the friendly Code Review server
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clk: msm: clock-cpu-titanium: Enable HF PLL early stage of boot 



At the early_initcall before we switch APSS RCG to source from APSS PLL,
make sure that the PLL is enabled. The boolean flags test_ctl_dbg and
init_test_ctl added to control the test bits of PLL.

Change-Id: I2189d72414de7fcce31e2686d7ba476928c5fa80
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 0e71a6df

drivers/clk/msm/clock-cpu-titanium.c

+3 −0
Original line number Diff line number Diff line
@@ -112,6 +112,8 @@ static struct pll_clk apcs_hf_pll = { 
	.test_ctl_lo_reg = (void __iomem *)APCS_PLL_TEST_CTL_LO,

	.test_ctl_hi_reg = (void __iomem *)APCS_PLL_TEST_CTL_HI,

	.status_reg = (void __iomem *)APCS_PLL_MODE,

	.init_test_ctl = true,

	.test_ctl_dbg = true,

	.masks = {

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),
@@ -937,6 +939,7 @@ static int __init cpu_clock_pwr_init(void) 


	__variable_rate_pll_init(&apcs_hf_pll.c);

	apcs_hf_pll.c.ops->set_rate(&apcs_hf_pll.c, pwrcl_early_boot_rate);

	clk_ops_variable_rate_pll.enable(&apcs_hf_pll.c);



	base = ioremap_nocache(APCS_ALIAS1_CMD_RCGR, SZ_8);

	regval = readl_relaxed(base);