msm: mdss: modify DSI phy init sequence for split-DSI config

For split-DSI hardware configuration, both the DSI controller clocks are
sourced from a single PLL (clock-master). In such cases, it is important
to initialize both DSI0 PHY and DSI1 PHY prior to enabling the PLL.
This is due to the fact that for certain HW versions, PLL programming
for the clock-master may require configure some PLL registers on the
clock-slave. If the PHY init sequence for the clock-slave is called
after PLL is programmed, it could reset those PLL registers leading to
unexpected behavior. Fix this by ensuring that PHY init sequence is done
for both controllers at the same time for split display usecases.

CRs-Fixed: 1000724
Change-Id: I09fb8097d31cd0390cea5c32bb7aabceeff2c37e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Signed-off-by: Ashish Garg <ashigarg@codeaurora.org>