qcom: clock-cpu-8994: Setup PLL dividers in early_init

As part of the CDIV divider workaround, we no longer
explicitly init the post-dividers until we actually
need to use the main output of the PLL to generate
frequencies less than 1.2Ghz. However, since the main
outputs are still enabled, the divider needs to be set
to div-2 even if we're running off the early output

Change-Id: Iff88dd722ab3356eb5a5957855be235596f951e2
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>