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Commit 6b74537a authored by Vikram Mulukutla's avatar Vikram Mulukutla
Browse files

clk: qcom: Modify the A57 don't-use-CDIV workaround 



The initial implementation of the A57 workaround to
avoid the use of the glitchy CDIV divider was to
eliminate the use of the frequencies below 600MHz
thus avoiding the need to program the CDIV.

In order to restore those frequency levels, use
the PLL post-divider setting of div-4 instead, and
raise the virtual corner vote for those frequencies
to match the power collapse frequency of 600Mhz.

Rework the clock tree sanity checking function a bit
to account for the duplicate virtual corner votes.

Change-Id: Ibb9a9de55ab2bf109de2cf4a439cc189e869c3de
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 5e498329

arch/arm/boot/dts/qcom/msm8994-v2.dtsi

+13 −1
Original line number Original line Diff line number Diff line
@@ -86,6 +86,8 @@ 
			< 1555200000 13>;

			< 1555200000 13>;

	qcom,a57-speedbin0-v0 =

	qcom,a57-speedbin0-v0 =

			<	   0 0>,

			<	   0 0>,

			<  384000000 5>,

			<  480000000 5>,

			<  633600000 5>,

			<  633600000 5>,

			<  768000000 6>,

			<  768000000 6>,

			<  864000000 7>,

			<  864000000 7>,
@@ -100,6 +102,8 @@ 
			< 1958400000 17>;

			< 1958400000 17>;

	qcom,a57-speedbin1-v0 =

	qcom,a57-speedbin1-v0 =

			<	   0 0>,

			<	   0 0>,

			<  384000000 5>,

			<  480000000 5>,

			<  633600000 5>,

			<  633600000 5>,

			<  768000000 6>,

			<  768000000 6>,

			<  864000000 7>,

			<  864000000 7>,
@@ -145,6 +149,8 @@ 
		< 1555200 >;

		< 1555200 >;





	qcom,cpufreq-table-4 =

	qcom,cpufreq-table-4 =

		<  384000 >,

		<  480000 >,

		<  633600 >,

		<  633600 >,

		<  768000 >,

		<  768000 >,

		<  864000 >,

		<  864000 >,
@@ -174,6 +180,8 @@ 
			< 1478400 11863 >,

			< 1478400 11863 >,

			< 1555200 11863 >;

			< 1555200 11863 >;

		cpu-to-dev-map-4 =

		cpu-to-dev-map-4 =

			<  384000  1525 >,

			<  480000  2288 >,

			<  633600  2288 >,

			<  633600  2288 >,

			<  768000  3509 >,

			<  768000  3509 >,

			<  864000  4066 >,

			<  864000  4066 >,
@@ -203,6 +211,8 @@ 
			< 1478400 5928 >,

			< 1478400 5928 >,

			< 1555200 5928 >;

			< 1555200 5928 >;

		cpu-to-dev-map-4 =

		cpu-to-dev-map-4 =

			<  384000 1525 >,

			<  480000 2288 >,

			<  633600 3509 >,

			<  633600 3509 >,

			<  768000 5126 >,

			<  768000 5126 >,

			<  864000 5928 >,

			<  864000 5928 >,
@@ -231,7 +241,9 @@ 
			< 1478400 787200 >,

			< 1478400 787200 >,

			< 1555200 787200 >;

			< 1555200 787200 >;

		cpu-to-dev-map-4 =

		cpu-to-dev-map-4 =

			<  633600 300000 >,

			<  384000 300000 >,

			<  480000 300000 >,

			<  633600 384000 >,

			<  768000 537600 >,

			<  768000 537600 >,

			<  864000 600000 >,

			<  864000 600000 >,

			<  960000 600000 >,

			<  960000 600000 >,

drivers/clk/qcom/clock-cpu-8994.c

+25 −14
Original line number Original line Diff line number Diff line
@@ -178,7 +178,6 @@ static struct pll_clk a57_pll0 = { 
	.pgm_test_ctl_enable = true,

	.pgm_test_ctl_enable = true,

	.masks = {

	.masks = {

		.pre_div_mask = BIT(12),

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),

		.mn_en_mask = BIT(24),

		.mn_en_mask = BIT(24),

		.main_output_mask = BIT(0),

		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.early_output_mask = BIT(3),
@@ -186,7 +185,6 @@ static struct pll_clk a57_pll0 = { 
		.lock_mask = BIT(31),

		.lock_mask = BIT(31),

	},

	},

	.vals = {

	.vals = {

		.post_div_masked = 0x100,

		.pre_div_masked = 0x0,

		.pre_div_masked = 0x0,

		.config_ctl_val = 0x000D6968,

		.config_ctl_val = 0x000D6968,

		.test_ctl_lo_val = 0x00010000,

		.test_ctl_lo_val = 0x00010000,
@@ -215,7 +213,6 @@ static struct pll_clk a57_pll1 = { 
	.pgm_test_ctl_enable = true,

	.pgm_test_ctl_enable = true,

	.masks = {

	.masks = {

		.pre_div_mask = BIT(12),

		.pre_div_mask = BIT(12),

		.post_div_mask = BM(9, 8),

		.mn_en_mask = BIT(24),

		.mn_en_mask = BIT(24),

		.main_output_mask = BIT(0),

		.main_output_mask = BIT(0),

		.early_output_mask = BIT(3),

		.early_output_mask = BIT(3),
@@ -223,7 +220,6 @@ static struct pll_clk a57_pll1 = { 
		.lock_mask = BIT(31),

		.lock_mask = BIT(31),

	},

	},

	.vals = {

	.vals = {

		.post_div_masked = 0x300,

		.pre_div_masked = 0x0,

		.pre_div_masked = 0x0,

		.config_ctl_val = 0x000D6968,

		.config_ctl_val = 0x000D6968,

		.test_ctl_lo_val = 0x00010000,

		.test_ctl_lo_val = 0x00010000,
@@ -703,6 +699,9 @@ static struct clk_div_ops pll_div_ops = { 
DEFINE_PLL_MUX_DIV(a53_pll0div_main, C0_PLL_BASE, &a53_pll0.c, C0_PLL_USER_CTL);

DEFINE_PLL_MUX_DIV(a53_pll0div_main, C0_PLL_BASE, &a53_pll0.c, C0_PLL_USER_CTL);

DEFINE_PLL_MUX_DIV(a53_pll1div_main, C0_PLL_BASE, &a53_pll1.c,

DEFINE_PLL_MUX_DIV(a53_pll1div_main, C0_PLL_BASE, &a53_pll1.c,

		   C0_PLLA_USER_CTL);

		   C0_PLLA_USER_CTL);

DEFINE_PLL_MUX_DIV(a57_pll0div_main, C1_PLL_BASE, &a57_pll0.c, C1_PLL_USER_CTL);

DEFINE_PLL_MUX_DIV(a57_pll1div_main, C1_PLL_BASE, &a57_pll1.c,

		   C1_PLLA_USER_CTL);





static struct mux_clk a53_lf_mux_v2 = {

static struct mux_clk a53_lf_mux_v2 = {

	.offset = MUX_OFFSET,

	.offset = MUX_OFFSET,
@@ -755,11 +754,12 @@ static struct mux_clk a57_lf_mux_v2 = { 
	.offset = MUX_OFFSET,

	.offset = MUX_OFFSET,

	MUX_SRC_LIST(

	MUX_SRC_LIST(

		{ &xo_ao.c,            0 },

		{ &xo_ao.c,            0 },

		{ &a57_pll1_main.c,   1 },

		{ &a57_pll1div_main.c, 1 },

		{ &a57_pll0_main.c,   2 },

		{ &a57_pll0div_main.c, 2 },

		{ &sys_apcsaux_clk.c,  3 },

		{ &sys_apcsaux_clk.c,  3 },

	),

	),

	.low_power_sel = 3,

	.low_power_sel = 3,

	.en_mask = 3,

	.ops = &cpu_mux_ops,

	.ops = &cpu_mux_ops,

	.mask = 0x3,

	.mask = 0x3,

	.shift = 1,

	.shift = 1,
@@ -782,6 +782,7 @@ static struct mux_clk a57_hf_mux_v2 = { 
		{ &a57_pll0.c,       3 },

		{ &a57_pll0.c,       3 },

	),

	),

	.low_power_sel = 0,

	.low_power_sel = 0,

	.en_mask = 0,

	.ops = &cpu_mux_ops,

	.ops = &cpu_mux_ops,

	.mask = 0x3,

	.mask = 0x3,

	.shift = 3,

	.shift = 3,
@@ -921,17 +922,17 @@ void sanity_check_clock_tree(u32 muxval, struct mux_clk *mux) 
	void *base = NULL;

	void *base = NULL;

	unsigned long rate;

	unsigned long rate;

	struct clk *c;

	struct clk *c;

	int cur_uv, req_uv;

	int *uv;





	if (!(msm8994_v2 || msm8992))

	if (!(msm8994_v2 || msm8992))

		return;

		return;





	if (mux->base == &vbases[ALIAS0_GLB_BASE]) {

	if (mux->base == &vbases[ALIAS0_GLB_BASE]) {

		level = a53_clk.c.vdd_class->cur_level;

		base = vbases[C0_PLL_BASE];

		base = vbases[C0_PLL_BASE];

		c = &a53_clk.c;

		c = &a53_clk.c;

	}

	}

	if (mux->base == &vbases[ALIAS1_GLB_BASE]) {

	if (mux->base == &vbases[ALIAS1_GLB_BASE]) {

		level = a57_clk.c.vdd_class->cur_level;

		base = vbases[C1_PLL_BASE];

		base = vbases[C1_PLL_BASE];

		c = &a57_clk.c;

		c = &a57_clk.c;

	}

	}
@@ -939,6 +940,13 @@ void sanity_check_clock_tree(u32 muxval, struct mux_clk *mux) 
	if (!base)

	if (!base)

		return;

		return;





	uv = c->vdd_class->vdd_uv;

	level = c->vdd_class->cur_level;



	/* Possibly hotplugged out */

	if (!level || !uv[level])

		return;



	switch (hfmux_sel) {

	switch (hfmux_sel) {

	case LFMUX_SEL:

	case LFMUX_SEL:

		switch (lfmux_sel) {

		switch (lfmux_sel) {
@@ -987,9 +995,13 @@ void sanity_check_clock_tree(u32 muxval, struct mux_clk *mux) 
	break;

	break;

	};

	};





	if (level < find_vdd_level(c, rate)) {

	/* One regulator */

		pr_err("rate is %lu, level is %d, cur level is %d\n", rate,

	cur_uv = uv[level];

			find_vdd_level(c, rate), level);

	req_uv = uv[find_vdd_level(c, rate)];



	if (cur_uv < req_uv) {

		pr_err("%s: rate is %lu, uv is %d, req uv is %d\n", c->dbg_name,

			rate, cur_uv, req_uv);

		BUG();

		BUG();

	}

	}

}

}
@@ -1591,7 +1603,6 @@ static void populate_opp_table(struct platform_device *pdev) 




static void init_v2_data(void)

static void init_v2_data(void)

{

{

	a57_pll1.vals.post_div_masked = 0x100;

	a53_pll0.vals.config_ctl_val = 0x004D6968;

	a53_pll0.vals.config_ctl_val = 0x004D6968;

	a53_pll1.vals.config_ctl_val = 0x004D6968;

	a53_pll1.vals.config_ctl_val = 0x004D6968;

	a57_pll0.vals.config_ctl_val = 0x004D6968;

	a57_pll0.vals.config_ctl_val = 0x004D6968;