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Commit c27a444e authored by Henrik Smiding's avatar Henrik Smiding Committed by Wang LiangX
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Add Silvermont architecture cache sizes 



Adds Silvermont specific cache sizes for memset16/32 SSE optimization.

Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70
Signed-off-by: default avatarHenrik Smiding <henrik.smiding@intel.com>
parent a740b3bb
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