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Commit c27a444e authored by Henrik Smiding's avatar Henrik Smiding Committed by Wang LiangX
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Add Silvermont architecture cache sizes 



Adds Silvermont specific cache sizes for memset16/32 SSE optimization.

Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70
Signed-off-by: default avatarHenrik Smiding <henrik.smiding@intel.com>
parent a740b3bb

libcutils/arch-x86/cache_wrapper.S

+9 −2
Original line number Original line Diff line number Diff line
@@ -17,8 +17,15 @@ 
 * Contributed by: Intel Corporation

 * Contributed by: Intel Corporation

 */

 */





#if defined(__slm__)

/* Values are optimized for Silvermont */

#define SHARED_CACHE_SIZE   (1024*1024)         /* Silvermont L2 Cache */

#define DATA_CACHE_SIZE     (24*1024)           /* Silvermont L1 Data Cache */

#else

/* Values are optimized for Atom */

/* Values are optimized for Atom */

#define SHARED_CACHE_SIZE   (512*1024)          /* Atom L2 Cache */

#define SHARED_CACHE_SIZE   (512*1024)          /* Atom L2 Cache */

#define DATA_CACHE_SIZE     (24*1024)           /* Atom L1 Data Cache */

#define DATA_CACHE_SIZE     (24*1024)           /* Atom L1 Data Cache */

#endif



#define SHARED_CACHE_SIZE_HALF  (SHARED_CACHE_SIZE / 2)

#define SHARED_CACHE_SIZE_HALF  (SHARED_CACHE_SIZE / 2)

#define DATA_CACHE_SIZE_HALF    (DATA_CACHE_SIZE / 2)
 
#define DATA_CACHE_SIZE_HALF    (DATA_CACHE_SIZE / 2)