ARM: dts: msm: Add property to not flush L1/L2 during power collapse

On 8939, the L1/L2 caches are flushed and invalidated by TZ. Add DT flag to
prevent flushing of L1/L2 cache during power collapse and update
corresponding latency parameters.

Change-Id: Idbbbccbaea9dee1f3b1d772637cb8a972016db23
Signed-off-by: Srinivas Rao L <lsrao@codeaurora.org>