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Commit 8dbea023 authored by Srinivas Rao L's avatar Srinivas Rao L Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add property to not flush L1/L2 during power collapse 



On 8939, the L1/L2 caches are flushed and invalidated by TZ. Add DT flag to
prevent flushing of L1/L2 cache during power collapse and update
corresponding latency parameters.

Change-Id: Idbbbccbaea9dee1f3b1d772637cb8a972016db23
Signed-off-by: default avatarSrinivas Rao L <lsrao@codeaurora.org>
parent 2bb25ecd

arch/arm/boot/dts/qcom/msm8939-pm.dtsi

+11 −9
Original line number Original line Diff line number Diff line
@@ -259,8 +259,8 @@ 
				qcom,spm-cci-mode = "active";

				qcom,spm-cci-mode = "active";

				qcom,latency-us = <750>;

				qcom,latency-us = <750>;

				qcom,ss-power = <575>;

				qcom,ss-power = <575>;

				qcom,energy-overhead = <1050000>;

				qcom,energy-overhead = <955000>;

				qcom,time-overhead = <1700>;

				qcom,time-overhead = <1540>;

			};

			};





			qcom,pm-cluster-level@1{

			qcom,pm-cluster-level@1{
@@ -269,8 +269,8 @@ 
				qcom,spm-cci-mode = "retention";

				qcom,spm-cci-mode = "retention";

				qcom,latency-us = <820>;

				qcom,latency-us = <820>;

				qcom,ss-power = <560>;

				qcom,ss-power = <560>;

				qcom,energy-overhead = <1330000>;

				qcom,energy-overhead = <1135000>;

				qcom,time-overhead = <1850>;

				qcom,time-overhead = <1800>;

				qcom,min-child-idx = <1>;

				qcom,min-child-idx = <1>;

			};

			};
@@ -280,7 +280,7 @@ 
				qcom,spm-cci-mode = "pc";

				qcom,spm-cci-mode = "pc";

				qcom,latency-us = <11500>;

				qcom,latency-us = <11500>;

				qcom,ss-power = <530>;

				qcom,ss-power = <530>;

				qcom,energy-overhead = <2514899>;

				qcom,energy-overhead = <2470000>;

				qcom,time-overhead = <3700>;

				qcom,time-overhead = <3700>;

				qcom,min-child-idx = <1>;

				qcom,min-child-idx = <1>;

				qcom,notify-rpm;

				qcom,notify-rpm;
@@ -311,8 +311,8 @@ 
					qcom,spm-l2-mode = "pc";

					qcom,spm-l2-mode = "pc";

					qcom,latency-us = <750>;

					qcom,latency-us = <750>;

					qcom,ss-power = <575>;

					qcom,ss-power = <575>;

					qcom,energy-overhead = <1050000>;

					qcom,energy-overhead = <955000>;

					qcom,time-overhead = <1700>;

					qcom,time-overhead = <1540>;

					qcom,min-child-idx = <2>;

					qcom,min-child-idx = <2>;

				};

				};
@@ -376,8 +376,8 @@ 
					qcom,spm-l2-mode = "pc";

					qcom,spm-l2-mode = "pc";

					qcom,latency-us = <600>;

					qcom,latency-us = <600>;

					qcom,ss-power = <574>;

					qcom,ss-power = <574>;

					qcom,energy-overhead = <1060000>;

					qcom,energy-overhead = <970000>;

					qcom,time-overhead = <1400>;

					qcom,time-overhead = <1260>;

					qcom,min-child-idx = <2>;

					qcom,min-child-idx = <2>;

				};

				};
@@ -580,6 +580,8 @@ 
			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_lc>,

			 <&clock_cpu clk_a53ssmux_cci>;

			 <&clock_cpu clk_a53ssmux_cci>;



		qcom,tz-flushes-cache;

	};

	};





	qcom,cpu-sleep-status@b088008{

	qcom,cpu-sleep-status@b088008{