Merge "ARM: dts: msm: add xo_clk for DSI display" (f2febc45) · Commits · e / devices / android_kernel_xiaomi_sm6125

arch/arm64/boot/dts/qcom/sa6155-display.dtsi

+3 −2

Original line number	Diff line number	Diff line
		@@ -179,8 +179,9 @@
		qcom,dsi-phy = <&mdss_dsi_phy0>;

		clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,
		<&mdss_dsi0_pll PIX0_MUX_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0";
		<&mdss_dsi0_pll PIX0_MUX_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0", "xo_clk";


		qcom,dsi-display-list =

arch/arm64/boot/dts/qcom/sa8155-adp-star-display.dtsi

+6 −4

Original line number	Diff line number	Diff line
		@@ -234,9 +234,10 @@
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1";
		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

		qcom,dsi-display-list =
		<&dsi_anx_7625_1>;
		@@ -264,9 +265,10 @@
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1";
		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

		qcom,dsi-display-list =
		<&dsi_anx_7625_2>;

arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi

+6 −4

Original line number	Diff line number	Diff line
		@@ -228,9 +228,10 @@
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1";
		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

		qcom,dsi-display-list =
		<&dsi_anx_7625_1>;
		@@ -258,9 +259,10 @@
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
		<&mdss_dsi0_pll PCLK_MUX_0_CLK>,
		<&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>;
		<&mdss_dsi1_pll PCLK_MUX_1_CLK>,
		<&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "mux_byte_clk0", "mux_pixel_clk0",
		"mux_byte_clk1", "mux_pixel_clk1";
		"mux_byte_clk1", "mux_pixel_clk1", "xo_clk";

		qcom,dsi-display-list =
		<&dsi_anx_7625_2>;

drivers/gpu/drm/msm/dsi-staging/dsi_display.c

+21 −7

Original line number	Diff line number	Diff line
		@@ -2282,11 +2282,20 @@ static int dsi_display_phy_power_off(struct dsi_display *display)
		return rc;
		}

		static int dsi_display_set_clk_src(struct dsi_display *display)
		static int dsi_display_set_clk_src(struct dsi_display *display, bool on)
		{
		int rc = 0;
		int i;
		struct dsi_display_ctrl m_ctrl, ctrl;
		struct dsi_clk_link_set *src;

		/* if XO clk is defined, select XO clk src when DSI is disabled */
		if (on)
		src = &display->clock_info.mux_clks;
		else if (display->clock_info.xo_clks.byte_clk)
		src = &display->clock_info.xo_clks;
		else
		return 0;

		/*
		* In case of split DSI usecases, the clock for master controller should
		@@ -2295,8 +2304,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
		*/
		m_ctrl = &display->ctrl[display->clk_master_idx];

		rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
		&display->clock_info.mux_clks);
		rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, src);
		if (rc) {
		pr_err("[%s] failed to set source clocks for master, rc=%d\n",
		display->name, rc);
		@@ -2309,8 +2317,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
		if (!ctrl->ctrl \|\| (ctrl == m_ctrl))
		continue;

		rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
		&display->clock_info.mux_clks);
		rc = dsi_ctrl_set_clock_source(ctrl->ctrl, src);
		if (rc) {
		pr_err("[%s] failed to set source clocks, rc=%d\n",
		display->name, rc);
		@@ -3000,12 +3007,17 @@ static int dsi_display_clocks_init(struct dsi_display *display)
		struct dsi_clk_link_set *src = &display->clock_info.src_clks;
		struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
		struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
		struct dsi_clk_link_set *xo = &display->clock_info.xo_clks;
		struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);

		num_clk = dsi_display_get_clocks_count(display);

		pr_debug("clk count=%d\n", num_clk);

		dsi_clk = devm_clk_get(&display->pdev->dev, "xo_clk");
		if (!IS_ERR_OR_NULL(dsi_clk))
		xo->byte_clk = xo->pixel_clk = dsi_clk;

		for (i = 0; i < num_clk; i++) {
		dsi_display_get_clock_name(display, i, &clk_name);

		@@ -6514,7 +6526,7 @@ static int dsi_display_pre_switch(struct dsi_display *display)
		goto error_ctrl_clk_off;
		}

		rc = dsi_display_set_clk_src(display);
		rc = dsi_display_set_clk_src(display, true);
		if (rc) {
		pr_err("[%s] failed to set DSI link clock source, rc=%d\n",
		display->name, rc);
		@@ -6906,7 +6918,7 @@ int dsi_display_prepare(struct dsi_display *display)
		}
		}

		rc = dsi_display_set_clk_src(display);
		rc = dsi_display_set_clk_src(display, true);
		if (rc) {
		pr_err("[%s] failed to set DSI link clock source, rc=%d\n",
		display->name, rc);
		@@ -7501,6 +7513,8 @@ int dsi_display_unprepare(struct dsi_display *display)
		pr_err("[%s] panel post-unprepare failed, rc=%d\n",
		display->name, rc);

		dsi_display_set_clk_src(display, false);

		mutex_unlock(&display->display_lock);

		/* Free up DSI ERROR event callback */

drivers/gpu/drm/msm/dsi-staging/dsi_display.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -115,11 +115,13 @@ struct dsi_display_boot_param {
		* @src_clks: Source clocks for DSI display.
		* @mux_clks: Mux clocks used for DFPS.
		* @shadow_clks: Used for DFPS.
		* @xo_clks: XO clocks for DSI display
		*/
		struct dsi_display_clk_info {
		struct dsi_clk_link_set src_clks;
		struct dsi_clk_link_set mux_clks;
		struct dsi_clk_link_set shadow_clks;
		struct dsi_clk_link_set xo_clks;
		};

		/**