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Commit 3d026858 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dsi-staging: add P/N swap support for DSI PHY"

parents ffb30e60 31740008

drivers/gpu/drm/msm/dsi-staging/dsi_phy.c

+33 −0
Original line number Diff line number Diff line
@@ -281,6 +281,32 @@ static int dsi_phy_parse_dt_per_lane_cfgs(struct platform_device *pdev, 
	return rc;

}



static int dsi_phy_parse_dt_per_lane_bits(struct platform_device *pdev,

					  u8 *bits,

					  char *property)

{

	int rc = 0, i = 0;

	const u8 *data;

	u32 len = 0;



	data = of_get_property(pdev->dev.of_node, property, &len);

	if (!data)

		return 0;



	if (len != DSI_LANE_MAX) {

		pr_err("incorrect phy %s settings, exp=%d, act=%d\n",

		       property, DSI_LANE_MAX, len);

		return -EINVAL;

	}



	*bits = 0;



	for (i = DSI_LOGICAL_LANE_0; i < DSI_LANE_MAX; i++)

		*bits |= (data[i] & 0x01) << i;



	return rc;

}



static int dsi_phy_settings_init(struct platform_device *pdev,

				 struct msm_dsi_phy *phy)

{
@@ -316,6 +342,13 @@ static int dsi_phy_settings_init(struct platform_device *pdev, 
		}

	}



	rc = dsi_phy_parse_dt_per_lane_bits(pdev, &phy->cfg.lane_pnswap,

					    "qcom,platform-lane-pnswap");

	if (rc) {

		pr_err("failed to parse lane P/N swap map, rc=%d\n", rc);

		goto err;

	}



	/* Actual timing values are dependent on panel */

	timing->count_per_lane = phy->ver_info->timing_cfg_count;

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h

+2 −0
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ struct dsi_phy_per_lane_cfgs { 
 * @regulators:       Regulator settings for lanes.

 * @pll_source:       PLL source.

 * @lane_map:         DSI logical to PHY lane mapping.

 * @lane_pnswap:      P/N swap status on each lane.

 * @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.

 * @bit_clk_rate_hz: DSI bit clk rate in HZ.

 */
@@ -105,6 +106,7 @@ struct dsi_phy_cfg { 
	struct dsi_phy_per_lane_cfgs regulators;

	enum dsi_phy_pll_source pll_source;

	struct dsi_lane_map lane_map;

	u8 lane_pnswap;

	bool force_clk_lane_hs;

	unsigned long bit_clk_rate_hz;

};

drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v4_0.c

+2 −1
Original line number Diff line number Diff line
@@ -131,7 +131,6 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
		 * to the logical data lane 0

		 */

		DSI_W32(phy, DSIPHY_LNX_LPRX_CTRL(i), 0);

		DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i), 0x0);

	}

	dsi_phy_hw_v4_0_config_lpcdrx(phy, cfg, true);
@@ -141,6 +140,8 @@ static void dsi_phy_hw_v4_0_lane_settings(struct dsi_phy_hw *phy, 
		DSI_W32(phy, DSIPHY_LNX_CFG1(i), cfg->lanecfg.lane[i][1]);

		DSI_W32(phy, DSIPHY_LNX_CFG2(i), cfg->lanecfg.lane[i][2]);

		DSI_W32(phy, DSIPHY_LNX_TX_DCTRL(i), tx_dctrl[i]);

		DSI_W32(phy, DSIPHY_LNX_PIN_SWAP(i),

					(cfg->lane_pnswap >> i) & 0x1);

	}



}