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Commit bdb3ae37 authored by Xiaowen Wu's avatar Xiaowen Wu Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add xo_clk for DSI display 



Add xo_clk support for DSI display to support hiberantion to disk.

Change-Id: Ie35c97e75555317876fd3837e5047a17cd19de8f
Signed-off-by: default avatarXiaowen Wu <wxiaowen@codeaurora.org>
parent 97108746

arch/arm64/boot/dts/qcom/sa6155-display.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -179,8 +179,9 @@ 
		qcom,dsi-phy = <&mdss_dsi_phy0>;



		clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,

			 <&mdss_dsi0_pll PIX0_MUX_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0";

			 <&mdss_dsi0_pll PIX0_MUX_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0", "xo_clk";





		qcom,dsi-display-list =

arch/arm64/boot/dts/qcom/sa8155-adp-star-display.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -234,9 +234,10 @@ 
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "mux_byte_clk1", "mux_pixel_clk1", "xo_clk";



		qcom,dsi-display-list =

			<&dsi_anx_7625_1>;
@@ -264,9 +265,10 @@ 
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "mux_byte_clk1", "mux_pixel_clk1", "xo_clk";



		qcom,dsi-display-list =

			<&dsi_anx_7625_2>;

arch/arm64/boot/dts/qcom/sa8195p-adp-star-display.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -228,9 +228,10 @@ 
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "mux_byte_clk1", "mux_pixel_clk1", "xo_clk";



		qcom,dsi-display-list =

			<&dsi_anx_7625_1>;
@@ -258,9 +259,10 @@ 
		clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,

			 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,

			 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;

			 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>;

		clock-names = "mux_byte_clk0", "mux_pixel_clk0",

			      "mux_byte_clk1", "mux_pixel_clk1";

			      "mux_byte_clk1", "mux_pixel_clk1", "xo_clk";



		qcom,dsi-display-list =

			<&dsi_anx_7625_2>;