clk: qcom: clk-cpu-qcs405: Add support for vdd_hf_pll regulator

HF PLL is connected to LDO5 for analog logic and CX for digital
logic. Thus the CPU driver should vote for both these rails when
there is a frequency request. Add support for voting to both
these rails.

Change-Id: I9ead650e8842272c31d7a99cacf1e3468af07aa3
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>