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Commit 94b969a3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "net: stmmac: Add support for 1.8/2.5V RGMII regulator"

parents 4781178d eac3c667

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

+110 −99
Original line number Diff line number Diff line
@@ -24,91 +24,7 @@ 
#include "dwmac-qcom-ethqos.h"

#include "stmmac_ptp.h"



#define RGMII_IO_MACRO_DEBUG1		0x20

#define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28



/* RGMII_IO_MACRO_CONFIG fields */

#define RGMII_CONFIG_FUNC_CLK_EN		BIT(30)

#define RGMII_CONFIG_POS_NEG_DATA_SEL		BIT(23)

#define RGMII_CONFIG_GPIO_CFG_RX_INT		GENMASK(21, 20)

#define RGMII_CONFIG_GPIO_CFG_TX_INT		GENMASK(19, 17)

#define RGMII_CONFIG_MAX_SPD_PRG_9		GENMASK(16, 8)

#define RGMII_CONFIG_MAX_SPD_PRG_2		GENMASK(7, 6)

#define RGMII_CONFIG_INTF_SEL			GENMASK(5, 4)

#define RGMII_CONFIG_BYPASS_TX_ID_EN		BIT(3)

#define RGMII_CONFIG_LOOPBACK_EN		BIT(2)

#define RGMII_CONFIG_PROG_SWAP			BIT(1)

#define RGMII_CONFIG_DDR_MODE			BIT(0)



/* SDCC_HC_REG_DLL_CONFIG fields */

#define SDCC_DLL_CONFIG_DLL_RST			BIT(30)

#define SDCC_DLL_CONFIG_PDN			BIT(29)

#define SDCC_DLL_CONFIG_MCLK_FREQ		GENMASK(26, 24)

#define SDCC_DLL_CONFIG_CDR_SELEXT		GENMASK(23, 20)

#define SDCC_DLL_CONFIG_CDR_EXT_EN		BIT(19)

#define SDCC_DLL_CONFIG_CK_OUT_EN		BIT(18)

#define SDCC_DLL_CONFIG_CDR_EN			BIT(17)

#define SDCC_DLL_CONFIG_DLL_EN			BIT(16)

#define SDCC_DLL_MCLK_GATING_EN			BIT(5)

#define SDCC_DLL_CDR_FINE_PHASE			GENMASK(3, 2)



/* SDCC_HC_REG_DDR_CONFIG fields */

#define SDCC_DDR_CONFIG_PRG_DLY_EN		BIT(31)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	GENMASK(26, 21)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	GENMASK(29, 27)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN	BIT(30)

#define SDCC_DDR_CONFIG_PRG_RCLK_DLY		GENMASK(8, 0)



/* SDCC_HC_REG_DLL_CONFIG2 fields */

#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS		BIT(21)

#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC		GENMASK(17, 10)

#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	GENMASK(3, 2)

#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW	BIT(1)

#define SDCC_DLL_CONFIG2_DDR_CAL_EN		BIT(0)



/* SDC4_STATUS bits */

#define SDC4_STATUS_DLL_LOCK			BIT(7)



/* RGMII_IO_MACRO_CONFIG2 fields */

#define RGMII_CONFIG2_RSVD_CONFIG15		GENMASK(31, 17)

#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG		BIT(16)

#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN	BIT(13)

#define RGMII_CONFIG2_CLK_DIVIDE_SEL		BIT(12)

#define RGMII_CONFIG2_RX_PROG_SWAP		BIT(7)

#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	BIT(6)

#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	BIT(5)



#define EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR 0x00000070

#define EMAC_HW_v2_3_2_RG 0x20030002



#define MII_BUSY 0x00000001

#define MII_WRITE 0x00000002



/* GMAC4 defines */

#define MII_GMAC4_GOC_SHIFT		2

#define MII_GMAC4_WRITE			BIT(MII_GMAC4_GOC_SHIFT)

#define MII_GMAC4_READ			(3 << MII_GMAC4_GOC_SHIFT)



#define MII_BUSY 0x00000001

#define MII_WRITE 0x00000002



#define DWC_ETH_QOS_PHY_INTR_STATUS     0x0013



#define LINK_UP 1

#define LINK_DOWN 0



#define LINK_DOWN_STATE 0x800

#define LINK_UP_STATE 0x400



#define MICREL_PHY_ID PHY_ID_KSZ9031

#define DWC_ETH_QOS_MICREL_PHY_INTCS 0x1b

#define DWC_ETH_QOS_MICREL_PHY_CTL 0x1f

#define DWC_ETH_QOS_MICREL_INTR_LEVEL 0x4000

#define DWC_ETH_QOS_BASIC_STATUS     0x0001

#define LINK_STATE_MASK 0x4

#define AUTONEG_STATE_MASK 0x20

#define MICREL_LINK_UP_INTR_STATUS BIT(0)



static unsigned long tlmm_central_base_addr;

bool phy_intr_en;



struct qcom_ethqos *pethqos;
@@ -197,7 +113,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	int retry = 1000;



	/* Set CDR_EN */

	if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

	if (ethqos->emac_ver == EMAC_HW_v2_3_2)

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);

	else
@@ -216,7 +132,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,

		      SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);



	if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {

	if (ethqos->emac_ver != EMAC_HW_v2_3_2) {

		rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,

			      0, SDCC_HC_REG_DLL_CONFIG);
@@ -256,7 +172,7 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos) 
	rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,

		      SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);



	if (ethqos->emac_ver != EMAC_HW_v2_3_2_RG) {

	if (ethqos->emac_ver != EMAC_HW_v2_3_2) {

		rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,

			      0, SDCC_HC_REG_DLL_CONFIG2);
@@ -307,7 +223,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      RGMII_IO_MACRO_CONFIG2);



		/* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,

				      69, SDCC_HC_REG_DDR_CONFIG);

		else
@@ -316,7 +232,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_DDR_CONFIG_PRG_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -344,7 +260,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      BIT(6), RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);
@@ -360,7 +276,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -381,7 +297,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      0, RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,

				      RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
@@ -395,7 +311,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
			      RGMII_IO_MACRO_CONFIG);

		rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,

			      0, RGMII_IO_MACRO_CONFIG2);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_CONFIG2_RX_PROG_SWAP,

				      RGMII_IO_MACRO_CONFIG2);
@@ -411,7 +327,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos) 
		rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,

			      SDCC_HC_REG_DDR_CONFIG);

		if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG)

		if (ethqos->emac_ver == EMAC_HW_v2_3_2)

			rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,

				      0, RGMII_IO_MACRO_CONFIG);

		else
@@ -927,6 +843,99 @@ static int emac_emb_smmu_cb_probe(struct platform_device *pdev) 
	return result;

}



static int ethqos_update_rgmii_tx_drv_strength(struct qcom_ethqos *ethqos)

{

	int ret = 0;

	struct resource *resource = NULL;

	struct platform_device *pdev = ethqos->pdev;

	struct net_device *dev = platform_get_drvdata(pdev);

	unsigned long tlmm_central_base = 0;

	unsigned long tlmm_central_size = 0;

	unsigned long reg_rgmii_io_pads_voltage = 0;



	resource =

	 platform_get_resource_byname(

	    ethqos->pdev, IORESOURCE_MEM, "tlmm-central-base");



	if (!resource) {

		ETHQOSINFO("Resource tlmm-central-base not found\n");

		goto err_out;

	}



	tlmm_central_base = resource->start;

	tlmm_central_size = resource_size(resource);

	ETHQOSDBG("tlmm_central_base = 0x%x, size = 0x%x\n",

		  tlmm_central_base, tlmm_central_size);



	tlmm_central_base_addr = (unsigned long)ioremap(

	   tlmm_central_base, tlmm_central_size);

	if ((void __iomem *)!tlmm_central_base_addr) {

		ETHQOSERR("cannot map dwc_tlmm_central reg memory, aborting\n");

		ret = -EIO;

		goto err_out;

	}



	ETHQOSDBG("dwc_tlmm_central = %#lx\n", tlmm_central_base_addr);



	reg_rgmii_io_pads_voltage =

	regulator_get_voltage(ethqos->reg_rgmii_io_pads);



	ETHQOSINFO("IOMACRO pads voltage: %u uV\n", reg_rgmii_io_pads_voltage);



	switch (reg_rgmii_io_pads_voltage) {

	case 1500000:

	case 1800000: {

		switch (ethqos->emac_ver) {

		case EMAC_HW_v2_0_0:

		case EMAC_HW_v2_2_0:

		case EMAC_HW_v2_3_2: {

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_WR(

				   TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_16MA,

				   TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_16MA,

				   TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_16MA);

				TLMM_RGMII_RX_HV_MODE_CTL_RGWR(0x0);

		}

		break;

		default:

		break;

		}

	}

	break;

	case 2500000:{

		switch (ethqos->emac_ver) {

		case EMAC_HW_v2_0_0:

		case EMAC_HW_v2_2_0:{

			if (ethqos->always_on_phy) {

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_WR(

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_16MA,

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA,

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA);

			} else if ((dev->phydev) &&

					(dev->phydev->phy_id ==

					ATH8035_PHY_ID)) {

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_WR(

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA,

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA,

				TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA);

			}

		}

		break;

		default:

		break;

		}

	}

	break;

	default:

	break;

	}



err_out:

	if (tlmm_central_base_addr)

		iounmap((void __iomem *)tlmm_central_base_addr);



	return ret;

}



static int qcom_ethqos_probe(struct platform_device *pdev)

{

	struct device_node *np = pdev->dev.of_node;
@@ -1010,20 +1019,22 @@ static int qcom_ethqos_probe(struct platform_device *pdev) 
		}

	}



	ethqos->emac_ver = rgmii_readl(ethqos,

				       EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);



	ethqos_update_rgmii_tx_drv_strength(ethqos);



	ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);

	if (ret)

		goto err_clk;



	ethqos->emac_ver = rgmii_readl(ethqos,

				       EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR);



	if (!ethqos_phy_intr_config(ethqos))

		ethqos_phy_intr_enable(ethqos);

	else

		ETHQOSERR("Phy interrupt configuration failed");

	rgmii_dump(ethqos);



	if (ethqos->emac_ver == EMAC_HW_v2_3_2_RG) {

	if (ethqos->emac_ver == EMAC_HW_v2_3_2) {

		ethqos_pps_irq_config(ethqos);

		create_pps_interrupt_device_node(&ethqos->avb_class_a_dev_t,

						 &ethqos->avb_class_a_cdev,

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.h

+176 −3
Original line number Diff line number Diff line
@@ -22,10 +22,10 @@ extern void *ipc_emac_log_ctxt; 


#define DRV_NAME "qcom-ethqos"

#define ETHQOSDBG(fmt, args...) \

	pr_debug(DRV_NAME " %s:%d " fmt, __func__, ## args)

	pr_debug(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)

#define ETHQOSERR(fmt, args...) \

do {\

	pr_err(DRV_NAME " %s:%d " fmt, __func__, ## args);\

	pr_err(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args);\

	if (ipc_emac_log_ctxt) { \

		ipc_log_string(ipc_emac_log_ctxt, \

		"%s: %s[%u]:[emac] ERROR:" fmt, __FILENAME__,\
@@ -33,7 +33,7 @@ do {\ 
	} \

} while (0)

#define ETHQOSINFO(fmt, args...) \

	pr_info(DRV_NAME " %s:%d " fmt, __func__, ## args)

	pr_info(DRV_NAME " %s:%d " fmt, __func__, __LINE__, ## args)

#define RGMII_IO_MACRO_CONFIG		0x0

#define SDCC_HC_REG_DLL_CONFIG		0x4

#define SDCC_HC_REG_DDR_CONFIG		0xC
@@ -65,6 +65,177 @@ do {\ 
#define AVB_CLASS_A_CHANNEL_NUM 2

#define AVB_CLASS_B_CHANNEL_NUM 3



#define RGMII_IO_MACRO_DEBUG1		0x20

#define EMAC_SYSTEM_LOW_POWER_DEBUG	0x28



/* RGMII_IO_MACRO_CONFIG fields */

#define RGMII_CONFIG_FUNC_CLK_EN		BIT(30)

#define RGMII_CONFIG_POS_NEG_DATA_SEL		BIT(23)

#define RGMII_CONFIG_GPIO_CFG_RX_INT		GENMASK(21, 20)

#define RGMII_CONFIG_GPIO_CFG_TX_INT		GENMASK(19, 17)

#define RGMII_CONFIG_MAX_SPD_PRG_9		GENMASK(16, 8)

#define RGMII_CONFIG_MAX_SPD_PRG_2		GENMASK(7, 6)

#define RGMII_CONFIG_INTF_SEL			GENMASK(5, 4)

#define RGMII_CONFIG_BYPASS_TX_ID_EN		BIT(3)

#define RGMII_CONFIG_LOOPBACK_EN		BIT(2)

#define RGMII_CONFIG_PROG_SWAP			BIT(1)

#define RGMII_CONFIG_DDR_MODE			BIT(0)



/* SDCC_HC_REG_DLL_CONFIG fields */

#define SDCC_DLL_CONFIG_DLL_RST			BIT(30)

#define SDCC_DLL_CONFIG_PDN			BIT(29)

#define SDCC_DLL_CONFIG_MCLK_FREQ		GENMASK(26, 24)

#define SDCC_DLL_CONFIG_CDR_SELEXT		GENMASK(23, 20)

#define SDCC_DLL_CONFIG_CDR_EXT_EN		BIT(19)

#define SDCC_DLL_CONFIG_CK_OUT_EN		BIT(18)

#define SDCC_DLL_CONFIG_CDR_EN			BIT(17)

#define SDCC_DLL_CONFIG_DLL_EN			BIT(16)

#define SDCC_DLL_MCLK_GATING_EN			BIT(5)

#define SDCC_DLL_CDR_FINE_PHASE			GENMASK(3, 2)



/* SDCC_HC_REG_DDR_CONFIG fields */

#define SDCC_DDR_CONFIG_PRG_DLY_EN		BIT(31)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY	GENMASK(26, 21)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE	GENMASK(29, 27)

#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN	BIT(30)

#define SDCC_DDR_CONFIG_PRG_RCLK_DLY		GENMASK(8, 0)



/* SDCC_HC_REG_DLL_CONFIG2 fields */

#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS		BIT(21)

#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC		GENMASK(17, 10)

#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL	GENMASK(3, 2)

#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW	BIT(1)

#define SDCC_DLL_CONFIG2_DDR_CAL_EN		BIT(0)



/* SDC4_STATUS bits */

#define SDC4_STATUS_DLL_LOCK			BIT(7)



/* RGMII_IO_MACRO_CONFIG2 fields */

#define RGMII_CONFIG2_RSVD_CONFIG15		GENMASK(31, 17)

#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG		BIT(16)

#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN	BIT(13)

#define RGMII_CONFIG2_CLK_DIVIDE_SEL		BIT(12)

#define RGMII_CONFIG2_RX_PROG_SWAP		BIT(7)

#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL	BIT(6)

#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN	BIT(5)



#define EMAC_I0_EMAC_CORE_HW_VERSION_RGOFFADDR 0x00000070



#define EMAC_HW_NONE 0

#define EMAC_HW_v2_0_0 0x20000000

#define EMAC_HW_v2_1_0 0x20010000

#define EMAC_HW_v2_2_0 0x20020000

#define EMAC_HW_v2_3_2 0x20030002



#define MII_BUSY 0x00000001

#define MII_WRITE 0x00000002



/* GMAC4 defines */

#define MII_GMAC4_GOC_SHIFT		2

#define MII_GMAC4_WRITE			BIT(MII_GMAC4_GOC_SHIFT)

#define MII_GMAC4_READ			(3 << MII_GMAC4_GOC_SHIFT)



#define MII_BUSY 0x00000001

#define MII_WRITE 0x00000002



#define DWC_ETH_QOS_PHY_INTR_STATUS     0x0013



#define LINK_UP 1

#define LINK_DOWN 0



#define LINK_DOWN_STATE 0x800

#define LINK_UP_STATE 0x400



#define ATH8031_PHY_ID 0x004dd074

#define ATH8035_PHY_ID 0x004dd072

#define QCA8337_PHY_ID 0x004dd036

#define ATH8030_PHY_ID 0x004dd076

#define MICREL_PHY_ID PHY_ID_KSZ9031

#define DWC_ETH_QOS_MICREL_PHY_INTCS 0x1b

#define DWC_ETH_QOS_MICREL_PHY_CTL 0x1f

#define DWC_ETH_QOS_MICREL_INTR_LEVEL 0x4000

#define DWC_ETH_QOS_BASIC_STATUS     0x0001

#define LINK_STATE_MASK 0x4

#define AUTONEG_STATE_MASK 0x20

#define MICREL_LINK_UP_INTR_STATUS BIT(0)



#define TLMM_BASE_ADDRESS (tlmm_central_base_addr)



#define TLMM_RGMII_HDRV_PULL_CTL1_ADDRESS_OFFSET\

	(((ethqos->emac_ver == EMAC_HW_v2_3_2) ? 0xA7000\

	 : (ethqos->emac_ver == EMAC_HW_v2_0_0) ? 0xA5000\

	 : (ethqos->emac_ver == EMAC_HW_v2_2_0) ? 0xA5000\

	 : 0))



#define TLMM_RGMII_HDRV_PULL_CTL1_ADDRESS\

	(((unsigned long *)\

		(TLMM_BASE_ADDRESS + TLMM_RGMII_HDRV_PULL_CTL1_ADDRESS_OFFSET)))



#define TLMM_RGMII_HDRV_PULL_CTL1_RGWR(data)\

	iowrite32(data,	(void __iomem *)TLMM_RGMII_HDRV_PULL_CTL1_ADDRESS)



#define TLMM_RGMII_HDRV_PULL_CTL1_RGRD(data)\

	((data) = ioread32((void __iomem *)TLMM_RGMII_HDRV_PULL_CTL1_ADDRESS))



#define TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK (unsigned long)(0x7)



#define TLMM_RGMII_HDRV_PULL_CTL1_CK_TX_HDRV_WR_MASK_15\

	(unsigned long)(0xFFFC7FFF)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_3_HDRV_WR_MASK_12\

	(unsigned long)(0xFFFF8FFF)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_2_HDRV_WR_MASK_9\

	(unsigned long)(0xFFFFF1FF)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_1_HDRV_WR_MASK_6\

	(unsigned long)(0xFFFFFE3F)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_0_HDRV_WR_MASK_3\

	(unsigned long)(0xFFFFFFC7)

#define TLMM_RGMII_HDRV_PULL_CTL1_CTL_TX_HDRV_WR_MASK_0\

	(unsigned long)(0xFFFFFFF8)



#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_2MA (unsigned long)(0x0)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_4MA (unsigned long)(0x1)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_6MA (unsigned long)(0x2)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_8MA (unsigned long)(0x3)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_10MA (unsigned long)(0x4)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_12MA (unsigned long)(0x5)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_14MA (unsigned long)(0x6)

#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_16MA (unsigned long)(0x7)



#define TLMM_RGMII_HDRV_PULL_CTL1_TX_HDRV_WR(clk, data, ctl) do {\

		unsigned long v;\

		unsigned long drv = data;\

		TLMM_RGMII_HDRV_PULL_CTL1_RGRD(v);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_CK_TX_HDRV_WR_MASK_15))\

		 | (((clk) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 15);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_TX_3_HDRV_WR_MASK_12))\

		 | (((drv) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 12);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_TX_2_HDRV_WR_MASK_9))\

		 | (((drv) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 9);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_TX_1_HDRV_WR_MASK_6))\

		 | (((drv) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 6);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_TX_0_HDRV_WR_MASK_3))\

		 | (((drv) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 3);\

		v = (v & (TLMM_RGMII_HDRV_PULL_CTL1_CTL_TX_HDRV_WR_MASK_0))\

		 | (((ctl) & (TLMM_RGMII_HDRV_PULL_CTL1_HDRV_MASK)) << 0);\

		TLMM_RGMII_HDRV_PULL_CTL1_RGWR(v);\

} while (0)



#define TLMM_RGMII_RX_HV_MODE_CTL_ADDRESS_OFFSET \

	(((ethqos->emac_ver == EMAC_HW_v2_3_2) ? 0xA7004\

	  : (ethqos->emac_ver == EMAC_HW_v2_0_0) ? 0xA5004\

	  : (ethqos->emac_ver == EMAC_HW_v2_2_0) ? 0xA5004\

	  : 0))



#define TLMM_RGMII_RX_HV_MODE_CTL_ADDRESS\

	((unsigned long *)\

	 (TLMM_BASE_ADDRESS + TLMM_RGMII_RX_HV_MODE_CTL_ADDRESS_OFFSET))\



#define TLMM_RGMII_RX_HV_MODE_CTL_RGWR(data)\

	(iowrite32(data, (void __iomem *)TLMM_RGMII_RX_HV_MODE_CTL_ADDRESS))



#define TLMM_RGMII_RX_HV_MODE_CTL_RGRD(data)\

	((data) = ioread32((void __iomem *)TLMM_RGMII_RX_HV_MODE_CTL_ADDRESS))



static inline u32 PPSCMDX(u32 x, u32 val)

{

	return (GENMASK(PPS_MINIDX(x) + 3, PPS_MINIDX(x)) &
@@ -145,6 +316,8 @@ struct qcom_ethqos { 
	unsigned long avb_class_a_intr_cnt;

	unsigned long avb_class_b_intr_cnt;

	struct dentry *debugfs_dir;



	int always_on_phy;

};



struct pps_cfg {

drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-gpio.c

+54 −21
Original line number Diff line number Diff line
@@ -89,7 +89,8 @@ int ethqos_init_reqgulators(struct qcom_ethqos *ethqos) 
	}



	if (of_property_read_bool(ethqos->pdev->dev.of_node,

				  "vreg_rgmii-supply")) {

				  "vreg_rgmii-supply") && (2500000 ==

		   regulator_get_voltage(ethqos->reg_rgmii_io_pads))) {

		ethqos->reg_rgmii =

		devm_regulator_get(&ethqos->pdev->dev, EMAC_VREG_RGMII_NAME);

		if (IS_ERR(ethqos->reg_rgmii)) {
@@ -189,21 +190,67 @@ void ethqos_free_gpios(struct qcom_ethqos *ethqos) 
	ethqos->gpio_phy_intr_redirect = -1;

}



int ethqos_init_gpio(struct qcom_ethqos *ethqos)

int ethqos_init_pinctrl(struct device *dev)

{

	struct pinctrl *pinctrl;

	struct pinctrl_state *emac_pps_0;

	struct pinctrl_state *pinctrl_state;

	int i = 0;

	int num_names;

	const char *name;

	int ret = 0;



	ethqos->gpio_phy_intr_redirect = -1;



	pinctrl = devm_pinctrl_get(&ethqos->pdev->dev);

	pinctrl = devm_pinctrl_get(dev);

	if (IS_ERR_OR_NULL(pinctrl)) {

		ret = PTR_ERR(pinctrl);

		ETHQOSERR("Failed to get pinctrl, err = %d\n", ret);

		return ret;

	}

	ETHQOSDBG("get pinctrl succeed\n");



	num_names = of_property_count_strings(dev->of_node, "pinctrl-names");

	if (num_names < 0) {

		dev_err(dev, "Cannot parse pinctrl-names: %d\n", num_names);

		return num_names;

	}



	for (i = 0; i < num_names; i++) {

		ret = of_property_read_string_index(

			dev->of_node, "pinctrl-names", i, &name);



		if (!strcmp(name, PINCTRL_STATE_DEFAULT))

			continue;



		pinctrl_state = pinctrl_lookup_state(pinctrl, name);

		if (IS_ERR_OR_NULL(pinctrl_state)) {

			ret = PTR_ERR(pinctrl_state);

			ETHQOSERR("lookup_state %s failed %d\n", name, ret);

			return ret;

		}



		ETHQOSINFO("pinctrl_lookup_state %s succeded\n", name);



		ret = pinctrl_select_state(pinctrl, pinctrl_state);

		if (ret) {

			ETHQOSERR("select_state %s failed %d\n", name, ret);

			return ret;

		}



		ETHQOSINFO("pinctrl_select_state %s succeded\n", name);

	}



	return ret;

}



int ethqos_init_gpio(struct qcom_ethqos *ethqos)

{

	int ret = 0;



	ethqos->gpio_phy_intr_redirect = -1;



	ret = ethqos_init_pinctrl(&ethqos->pdev->dev);

	if (ret) {

		ETHQOSERR("ethqos_init_pinctrl failed");

		return ret;

	}



	ret = setup_gpio_input_common(

			&ethqos->pdev->dev, "qcom,phy-intr-redirect",
@@ -215,20 +262,6 @@ int ethqos_init_gpio(struct qcom_ethqos *ethqos) 
		goto gpio_error;

	}



	emac_pps_0 = pinctrl_lookup_state(pinctrl, EMAC_PIN_PPS0);

	if (IS_ERR_OR_NULL(emac_pps_0)) {

		ret = PTR_ERR(emac_pps_0);

		ETHQOSERR("Failed to get emac_pps_0, err = %d\n", ret);

		return ret;

	}

	ETHQOSDBG("Get emac_pps_0 succeed\n");

	ret = pinctrl_select_state(pinctrl, emac_pps_0);

	if (ret)

		ETHQOSERR("Unable to set emac_pps_0 state, err = %d\n",

			  ret);

	else

		ETHQOSDBG("Set emac_pps_0 succeed\n");



	return ret;



gpio_error: