msm: adreno: add support for array based acd-levels for a640

A640 has two ACD levels in a array, ACDCR and ACDTD, as per new change
if we give gmu firmware only ACDCR on A640, it fails to work,
so add back support for parsing both CR and TD while keeping current implementation.

removed in following commit:
<cc4d8f7b msm: kgsl: Add support for speedbin specific acd table>