msm: ep_pcie: Update PCIe WAKE# GPIO behaviour

Currently when there is a need to send WAKE# GPIO from device
to host during D3_COLD the WAKE# GPIO is toggled. However during
sleep use case the PDC is unable to detect the toggle that
results in the pulse. Therefore drive the GPIO high after L0
and keep it high until device needs to send a WAKE# request to
the host. Host detects the falling edge for the WAKE# to initiate
the link back to L0.

Change-Id: I92639bdae72ba51a4fbb00a7a763eae352966ac6
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>