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Commit 1a3c6dad authored by Siddartha Mohanadoss's avatar Siddartha Mohanadoss
Browse files

msm: ep_pcie: Update PCIe WAKE# GPIO behaviour 



Currently when there is a need to send WAKE# GPIO from device
to host during D3_COLD the WAKE# GPIO is toggled. However during
sleep use case the PDC is unable to detect the toggle that
results in the pulse. Therefore drive the GPIO high after L0
and keep it high until device needs to send a WAKE# request to
the host. Host detects the falling edge for the WAKE# to initiate
the link back to L0.

Change-Id: I92639bdae72ba51a4fbb00a7a763eae352966ac6
Signed-off-by: default avatarSiddartha Mohanadoss <smohanad@codeaurora.org>
parent b5babf58

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+11 −2
Original line number Diff line number Diff line
@@ -1632,6 +1632,14 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) 
	}



checkbme:

	/*

	 * De-assert WAKE# GPIO following link until L2/3 and WAKE#

	 * is triggered to send data from device to host at which point

	 * it will assert WAKE#.

	 */

	gpio_set_value(dev->gpio[EP_PCIE_GPIO_WAKE].num,

			1 - dev->gpio[EP_PCIE_GPIO_WAKE].on);



	if (dev->active_config)

		ep_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x14);
@@ -2621,8 +2629,9 @@ static int ep_pcie_core_wakeup_host(enum ep_pcie_event event) 
		dev->rev, dev->wake_counter,

		dev->perst_deast ? "" : "not",

		dev->l23_ready ? "" : "not");

	gpio_set_value(dev->gpio[EP_PCIE_GPIO_WAKE].num,

			1 - dev->gpio[EP_PCIE_GPIO_WAKE].on);

	/*

	 * Assert WAKE# GPIO until link is back to L0.

	 */

	gpio_set_value(dev->gpio[EP_PCIE_GPIO_WAKE].num,

			dev->gpio[EP_PCIE_GPIO_WAKE].on);

	return 0;