clk: msm: clock: Add additional delay while enabling votable clocks

During the GDSC enable sequence, the GDS_HW_CTRL forces some
clocks to be on to trigger the handshake to unhalt the SMMU
and NOC. Once the handshake completes, the controller asserts
the PWR_ON status and disables the clocks.
If the clock driver tries enabling the SMMU ahb/axi clocks
immediately, there is a possibility that these clocks might
still not have gone through their disable sequence; especially
if the AXI/AHB rates are very low. If this happens, the clock
driver falsely assumes that the clocks are on and returns. Any
SMMU accesses/trafic at this point might lead to a failure since
the clock could turn off.

Change-Id: I1ab39be9afd48681f8d1f122dfdd7b40cbef06c3
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>