Commit ecdcb85f authored Oct 02, 2015 by Deepak Katragadda

clk: msm: clock: Add additional delay while enabling votable clocks



During the GDSC enable sequence, the GDS_HW_CTRL forces some
clocks to be on to trigger the handshake to unhalt the SMMU
and NOC. Once the handshake completes, the controller asserts
the PWR_ON status and disables the clocks.
If the clock driver tries enabling the SMMU ahb/axi clocks
immediately, there is a possibility that these clocks might
still not have gone through their disable sequence; especially
if the AXI/AHB rates are very low. If this happens, the clock
driver falsely assumes that the clocks are on and returns. Any
SMMU accesses/trafic at this point might lead to a failure since
the clock could turn off.

Change-Id: I1ab39be9afd48681f8d1f122dfdd7b40cbef06c3
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>

parent c57b8e5f

drivers/clk/msm/clock-local2.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -634,6 +634,14 @@ static int branch_clk_enable(struct clk *c)
		writel_relaxed(cbcr_val, CBCR_REG(branch));
		spin_unlock_irqrestore(&local_clock_reg_lock, flags);

		/*
		* For clocks controlled by other masters via voting registers,
		* delay polling for the status bit to allow previous clk_disable
		* by the GDS controller to go through.
		*/
		if (branch->no_halt_check_on_disable)
		udelay(5);

		/* Wait for clock to enable before continuing. */
		branch_clk_halt_check(c, branch->halt_check, CBCR_REG(branch),
		BRANCH_ON);