ARM: dts: msm: Update minbw table for MSM8996 to improve performance

This update ensures that there is no performance degradation due to the
bus/DDR running slow when there is at least a single threaded workload
that's keeps the CPU completely busy but has sporadic low bandwidth memory
access due to infrequent cache misses.

Change-Id: Ib0302eb5c2d9a1d6d7e6827ceed5cc67ef5070ec
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>