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Commit cebb6e1f authored by Taniya Das's avatar Taniya Das
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clk: msm: clock-gcc: Fix the divider values for blsp uart clock 



The M & N divider values to generate 64MHz was incorrect for MSMGold, fix
the same.

Change-Id: I0461b7e1830dd2ccf22fb6c87f37678d1a092061
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 60235d3d
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