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Commit cebb6e1f authored by Taniya Das's avatar Taniya Das
Browse files

clk: msm: clock-gcc: Fix the divider values for blsp uart clock 



The M & N divider values to generate 64MHz was incorrect for MSMGold, fix
the same.

Change-Id: I0461b7e1830dd2ccf22fb6c87f37678d1a092061
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 60235d3d

drivers/clk/msm/clock-gcc-8952.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -917,7 +917,7 @@ static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = { 
	F( 56000000,	gpll0,	1,	7,	100),

	F( 56000000,	gpll0,	1,	7,	100),

	F( 58982400,	gpll0,	1,	1152,	15625),

	F( 58982400,	gpll0,	1,	1152,	15625),

	F( 60000000,	gpll0,	1,	3,	40),

	F( 60000000,	gpll0,	1,	3,	40),

	F( 64000000,	gpll0, 12,	1,	 2),

	F( 64000000,	gpll0,  1,	2,	25),

	F_END

	F_END

};

};