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Commit 9170257e authored by Vikram Mulukutla's avatar Vikram Mulukutla Committed by Matt Wagantall
Browse files

clk: msm: clock-pll: Allow for additional initial config 



Some chipsets need additional setup for PLLs - these
settings are in "expert" registers that are beyond the
scope of SW. Add support to program these settings.

Change-Id: I3f82df4db9039ea7bd48641f8690c2bbaabfc2b5
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent eee8a59f

drivers/clk/msm/clock-pll.c

+5 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 
							(x)->config_alt_reg)

#define PLL_CFG_CTL_REG(x)	(*(x)->base + (unsigned long) \

							(x)->config_ctl_reg)

#define PLL_CFG_CTL_HI_REG(x)	(*(x)->base + (unsigned long) \

							(x)->config_ctl_hi_reg)

#define PLL_TEST_CTL_LO_REG(x)	(*(x)->base + (unsigned long) \

							(x)->test_ctl_lo_reg)

#define PLL_TEST_CTL_HI_REG(x)	(*(x)->base + (unsigned long) \
@@ -243,6 +245,9 @@ void __variable_rate_pll_init(struct clk *c) 


	writel_relaxed(pll->vals.alpha_val, PLL_ALPHA_REG(pll));

	writel_relaxed(pll->vals.config_ctl_val, PLL_CFG_CTL_REG(pll));

	if (pll->vals.config_ctl_hi_val)

		writel_relaxed(pll->vals.config_ctl_hi_val,

				PLL_CFG_CTL_HI_REG(pll));

	if (pll->init_test_ctl) {

		writel_relaxed(pll->vals.test_ctl_lo_val,

				PLL_TEST_CTL_LO_REG(pll));

include/soc/qcom/clock-pll.h

+4 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ struct pll_config_vals { 
	u32 post_div_masked;

	u32 pre_div_masked;

	u32 config_ctl_val;

	u32 config_ctl_hi_val;

	u32 test_ctl_lo_val;

	u32 test_ctl_hi_val;

	u32 alpha_val;
@@ -115,6 +116,8 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c) 
 * @config_reg: configuration register, contains mn divider enable, pre divider,

 *   post divider and vco configuration. register name can be configure register

 *   or user_ctl register depending on targets

 * @config_ctl_reg: "expert" configuration register

 * @config_ctl_hi_reg: upper 32 bits of the "expert" configuration register

 * @status_reg: status register, contains the lock detection bit

 * @init_test_ctl: initialize the test control register

 * @pgm_test_ctl_enable: program the test_ctl register in the enable sequence
@@ -133,6 +136,7 @@ struct pll_clk { 
	void __iomem *const alpha_reg;

	void __iomem *const config_reg;

	void __iomem *const config_ctl_reg;

	void __iomem *const config_ctl_hi_reg;

	void __iomem *const status_reg;

	void __iomem *const test_ctl_lo_reg;

	void __iomem *const test_ctl_hi_reg;