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Commit eee8a59f authored by Vikram Mulukutla's avatar Vikram Mulukutla Committed by Matt Wagantall
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clk: msm: clock-alpha-pll: Allow for additional initial config 



Some chipsets need additional setup for PLLs - these
settings are in "expert" registers that are beyond the
scope of SW. Add support to program these settings.

Change-Id: Ibcdbad49d53ed00f7a2cb6a2fd448394f186955c
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent 143c9e5e

drivers/clk/msm/clock-alpha-pll.c

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#define OUTPUT_REG(pll) (*pll->base + pll->offset + 0x10)

#define VOTE_REG(pll) (*pll->base + pll->fsm_reg_offset)

#define USER_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x10)

#define CONFIG_CTL_REG(pll) (*pll->base + pll->offset + 0x18)



#define PLL_BYPASSNL 0x2

#define PLL_RESET_N  0x4
@@ -451,6 +452,9 @@ void __init_alpha_pll(struct clk *c) 
	struct alpha_pll_masks *masks = pll->masks;

	u32 output_en, userval;



	if (pll->config_ctl_val)

		writel_relaxed(pll->config_ctl_val, CONFIG_CTL_REG(pll));



	if (masks->output_mask && pll->enable_config) {

		output_en = readl_relaxed(OUTPUT_REG(pll));

		output_en &= ~masks->output_mask;

include/soc/qcom/clock-alpha-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ struct alpha_pll_clk { 


	u32 enable_config;	/* bitmask of outputs to be enabled */

	u32 post_div_config;	/* masked post divider setting */

	u32 config_ctl_val;	/* config register init value */



	struct alpha_pll_vco_tbl *vco_tbl;

	u32 num_vco;