clk: msm: clock-pll: Support hardware FSM mode

Some PLL implementations support HW control of PLLs,
and it is expected that software does not enable
or disable the PLLs explicitly. Everything else
with respect to PLL configuration remains the same.

Note that this is different from the FSM mode where
software enables/disables the PLL using a vote
register.

Change-Id: I02d5c3112c445a25027afa8adb619582dde5f895
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>