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Commit 7b41acfb authored by Dhaval Patel's avatar Dhaval Patel
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Revert "msm: mdss: handle mmagic mdss axi clock for msm8996 target" 



This reverts commit 832b482b ("msm: mdss: handle mmagic mdss
axi clock for msm8996 target"). SMMU driver adds the vote for
mmagic mdss axi clock vote which will take care of MDP and
DSI use cases. No need to put vote from individual module.

Change-Id: I858f28eb88deb34a612050d913459e62cc0955a8
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
parent 393f8478

arch/arm/boot/dts/qcom/msm8996-mdss.dtsi

+2 −3
Original line number Diff line number Diff line
@@ -103,10 +103,9 @@ 
			 <&clock_mmss clk_mdss_axi_clk>,

			 <&clock_mmss clk_mdp_clk_src>,

			 <&clock_mmss clk_mdss_mdp_vote_clk>,

			 <&clock_mmss clk_mdss_vsync_clk>,

			 <&clock_mmss clk_mmagic_mdss_axi_clk>;

			 <&clock_mmss clk_mdss_vsync_clk>;

		clock-names = "iface_clk", "bus_clk", "core_clk_src",

				"core_clk", "vsync_clk", "mmagic_mdss_axi_clk";

				"core_clk", "vsync_clk";



		qcom,mdp-settings = <0x01190 0x00000000>,

				    <0x012ac 0xc0000ccc>,

drivers/video/msm/mdss/mdss.h

+0 −1
Original line number Diff line number Diff line
@@ -40,7 +40,6 @@ enum mdss_mdp_clk_type { 
	MDSS_CLK_MDP_CORE,

	MDSS_CLK_MDP_LUT,

	MDSS_CLK_MDP_VSYNC,

	MDSS_CLK_MMAGIC_AXI,

	MDSS_MAX_CLK

};

drivers/video/msm/mdss/mdss_mdp.c

+0 −4
Original line number Diff line number Diff line
@@ -854,7 +854,6 @@ void mdss_mdp_clk_ctrl(int enable) 
		mdss_mdp_clk_update(MDSS_CLK_AXI, enable);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable);

		mdss_mdp_clk_update(MDSS_CLK_MDP_LUT, enable);

		mdss_mdp_clk_update(MDSS_CLK_MMAGIC_AXI, enable);

		if (mdata->vsync_ena)

			mdss_mdp_clk_update(MDSS_CLK_MDP_VSYNC, enable);
@@ -994,9 +993,6 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) 
	/* vsync_clk is optional for non-smart panels */

	mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC);



	mdss_mdp_irq_clk_register(mdata, "mmagic_mdss_axi_clk",

		MDSS_CLK_MMAGIC_AXI);



	/* Setting the default clock rate to the max supported.*/

	mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate);

	pr_debug("mdp clk rate=%ld\n",