Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 832b482b authored by Dhaval Patel's avatar Dhaval Patel Committed by Matt Wagantall
Browse files

msm: mdss: handle mmagic mdss axi clock for thulium target 



MDSS module needs turn on mmagic AXI clock on thulium target
when it tries to fetch data or write data to output buffers.
This change adds that support.

Change-Id: I3e84046274d377c30028608217247bdfb32bc341
[veeras@codeaurora.org: As part of 3.18 upgrade,
remove msmthulium-mdss.dtsi changes from this commit]
Signed-off-by: default avatarDhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent 6faf4b4e

drivers/video/msm/mdss/mdss.h

+1 −0
Original line number Diff line number Diff line
@@ -38,6 +38,7 @@ enum mdss_mdp_clk_type { 
	MDSS_CLK_MDP_CORE,

	MDSS_CLK_MDP_LUT,

	MDSS_CLK_MDP_VSYNC,

	MDSS_CLK_MMAGIC_AXI,

	MDSS_MAX_CLK

};

drivers/video/msm/mdss/mdss_mdp.c

+4 −0
Original line number Diff line number Diff line
@@ -783,6 +783,7 @@ void mdss_mdp_clk_ctrl(int enable) 
		mdss_mdp_clk_update(MDSS_CLK_AXI, enable);

		mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable);

		mdss_mdp_clk_update(MDSS_CLK_MDP_LUT, enable);

		mdss_mdp_clk_update(MDSS_CLK_MMAGIC_AXI, enable);

		if (mdata->vsync_ena)

			mdss_mdp_clk_update(MDSS_CLK_MDP_VSYNC, enable);
@@ -910,6 +911,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) 
	/* vsync_clk is optional for non-smart panels */

	mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC);



	mdss_mdp_irq_clk_register(mdata, "mmagic_mdss_axi_clk",

		MDSS_CLK_MMAGIC_AXI);



	/* Setting the default clock rate to the max supported.*/

	mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate);

	pr_debug("mdp clk rate=%ld\n", mdss_mdp_get_clk_rate(MDSS_CLK_MDP_SRC));