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Commit 59d29328 authored by Trilok Soni's avatar Trilok Soni
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edac: cortex: Add EDAC L1 and L2 error reporting for Kryo2xx Silver CPUs 



Kryo2xx Silver CPUs support L1 and L2 cache error reporting. Add
support for the same.

CRs-Fixed: 969563
Change-Id: Ia2c860803169843a227eacebc9869e11673ffc7a
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 612c2fb8
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