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Commit 59d29328 authored by Trilok Soni's avatar Trilok Soni
Browse files

edac: cortex: Add EDAC L1 and L2 error reporting for Kryo2xx Silver CPUs 



Kryo2xx Silver CPUs support L1 and L2 cache error reporting. Add
support for the same.

CRs-Fixed: 969563
Change-Id: Ia2c860803169843a227eacebc9869e11673ffc7a
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
parent 612c2fb8

drivers/edac/cortex_arm64_edac.c

+2 −0
Original line number Diff line number Diff line
@@ -575,6 +575,7 @@ static void arm64_erp_local_handler(void *info) 


	switch (partnum) {

	case ARM_CPU_PART_CORTEX_A53:

	case ARM_CPU_PART_KRYO2XX_SILVER:

		ca53_parse_cpumerrsr(errdata);

		ca53_parse_l2merrsr(errdata);

	break;
@@ -745,6 +746,7 @@ static void check_sbe_event(struct erp_drvdata *drv) 
	spin_lock_irqsave(&local_handler_lock, flags);

	switch (partnum) {

	case ARM_CPU_PART_CORTEX_A53:

	case ARM_CPU_PART_KRYO2XX_SILVER:

		ca53_parse_cpumerrsr(&errdata);

		ca53_parse_l2merrsr(&errdata);

	break;