ARM: dts: msm: reduce VDD_APCC voltage margin for aging on msm8996v3

Reduce the VDD_APCC open-loop voltage margin by 15 mV and the
closed-loop voltage margin by 10 mV for power cluster and
performance cluster corners corresponding to less than 600 MHz.

Also, reduce the VDD_APCC open-loop voltage margin by 15 mV and
the closed-loop voltage margin by 10 mV for all CBF clock
corners.

This removes the voltage margin associated with aging and allows
lower VDD_APCC operating voltage are parts that are not aged.

Change-Id: I243000f8f277e0284d9c87d11c2c50ec9e280a00
Signed-off-by: David Collins <collinsd@codeaurora.org>