Commit 1f339fb0 authored Oct 07, 2015 by Susheel Khiani

ARM: dts: msm: Ensure access control is always last context bank



In situation like pre-silicon when TZ image is not
available we allow HLOS to go ahead and program SMR
and S2CR registers during 1st attach call. In cases
where we have access_control CB, we call iommu_attach
immediately after access_control CB probe. Now if
iommu_attach is called before probing of all the
context banks we end up getting NULL ctx_drvdata
structure for all the CBs which are still to be
probed. As a result we end up getting NULL pointer
derefence error when going to program global registers.
So ensure that access_control is always the last
CB to be probed.

Change-Id: I71e49d051cba3fa3080b5c1a05205b5a61ec0c82
Signed-off-by: Susheel Khiani <skhiani@codeaurora.org>

parent 5d328014

arch/arm/boot/dts/qcom/msm-arm-smmu-titanium.dtsi

+9 −9

Original line number	Diff line number	Diff line
		@@ -237,6 +237,15 @@
		qcom,report-error-on-fault;
		};

		ipa: qcom,iommu-ctx@1e38000 {
		compatible = "qcom,msm-smmu-v2-ctx";
		reg = <0x1e38000 0x1000>;
		interrupts = <0 115 0>;
		qcom,iommu-ctx-sids = <0x2000 0x2004>;
		qcom,iommu-sid-mask = <0x3fa 0x3f8>;
		label = "ipa";
		};

		access_control: qcom,iommu-ctx@1e37000 {
		compatible = "qcom,msm-smmu-v2-ctx";
		reg = <0x1e37000 0x1000>;
		@@ -247,15 +256,6 @@
		0x7f 0x1 0x1 0x3f>;
		label = "access_control";
		};

		ipa: qcom,iommu-ctx@1e38000 {
		compatible = "qcom,msm-smmu-v2-ctx";
		reg = <0x1e38000 0x1000>;
		interrupts = <0 115 0>;
		qcom,iommu-ctx-sids = <0x2000 0x2004>;
		qcom,iommu-sid-mask = <0x3fa 0x3f8>;
		label = "ipa";
		};
		};
		};