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Commit ce1d30b5 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Set UCHE_CACHE_WAYS_VFD to 0x7 for A3XX"

parents f9f7494b 79f578a7

drivers/gpu/msm/a3xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -334,6 +334,7 @@ 
#define A3XX_UCHE_PERFCOUNTER4_SELECT 0xE88

#define A3XX_UCHE_PERFCOUNTER5_SELECT 0xE89

#define A3XX_UCHE_CACHE_INVALIDATE0_REG 0xEA0

#define A3XX_UCHE_CACHE_WAYS_VFD 0xEA6

#define A3XX_SP_PERFCOUNTER0_SELECT 0xEC4

#define A3XX_SP_PERFCOUNTER1_SELECT 0xEC5

#define A3XX_SP_PERFCOUNTER2_SELECT 0xEC6

drivers/gpu/msm/adreno_a3xx.c

+3 −0
Original line number Diff line number Diff line
@@ -2274,6 +2274,9 @@ static void a3xx_start(struct adreno_device *adreno_dev) 
	/* Enable 64-byte cacheline size. HW Default is 32-byte (0x000000E0). */

	kgsl_regwrite(device, A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001);



	/* Enable VFD to access most of the UCHE (7 ways out of 8) */

	kgsl_regwrite(device, A3XX_UCHE_CACHE_WAYS_VFD, 0x07);



	/* Enable Clock gating */

	kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL,

		adreno_a3xx_rbbm_clock_ctl_default(adreno_dev));