Loading drivers/gpu/msm/a4xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -522,6 +522,7 @@ enum a4xx_sp_perfctr_sp_sel { #define UCHE_TRAP_BASE_HI 0xe84 #define A4XX_UCHE_INVALIDATE0 0xe8a #define A4XX_UCHE_INVALIDATE1 0xe8b #define A4XX_UCHE_CACHE_WAYS_VFD 0xe8c /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 Loading drivers/gpu/msm/adreno_a4xx.c +3 −0 Original line number Diff line number Diff line Loading @@ -586,6 +586,9 @@ static void a4xx_start(struct adreno_device *adreno_dev) /* Turn on the GPU busy counter and let it run free */ memset(&adreno_dev->busy_data, 0, sizeof(adreno_dev->busy_data)); /* Enable VFD to access most of the UCHE (7 ways out of 8) */ kgsl_regwrite(device, A4XX_UCHE_CACHE_WAYS_VFD, 0x07); /* Disable L2 bypass to avoid UCHE out of bounds errors */ kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000); kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); Loading Loading
drivers/gpu/msm/a4xx_reg.h +1 −0 Original line number Diff line number Diff line Loading @@ -522,6 +522,7 @@ enum a4xx_sp_perfctr_sp_sel { #define UCHE_TRAP_BASE_HI 0xe84 #define A4XX_UCHE_INVALIDATE0 0xe8a #define A4XX_UCHE_INVALIDATE1 0xe8b #define A4XX_UCHE_CACHE_WAYS_VFD 0xe8c /* VSC registers */ #define A4XX_VSC_SIZE_ADDRESS 0xc01 Loading
drivers/gpu/msm/adreno_a4xx.c +3 −0 Original line number Diff line number Diff line Loading @@ -586,6 +586,9 @@ static void a4xx_start(struct adreno_device *adreno_dev) /* Turn on the GPU busy counter and let it run free */ memset(&adreno_dev->busy_data, 0, sizeof(adreno_dev->busy_data)); /* Enable VFD to access most of the UCHE (7 ways out of 8) */ kgsl_regwrite(device, A4XX_UCHE_CACHE_WAYS_VFD, 0x07); /* Disable L2 bypass to avoid UCHE out of bounds errors */ kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000); kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000); Loading