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Commit 08b767ce authored by Kevin Matlage's avatar Kevin Matlage
Browse files

msm: kgsl: Set UCHE_CACHE_WAYS_VFD to 0x7 for A4XX 



This setting allows VFD to access most of UCHE
(7 of the 8 ways), which can increase performance
in some vertex-heavy cases.

Change-Id: I08e21f1408f682e996e29ede591593f8c27ba413
Signed-off-by: default avatarKevin Matlage <kmatlage@codeaurora.org>
parent beaca7d7

drivers/gpu/msm/a4xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -513,6 +513,7 @@ enum a4xx_sp_perfctr_sp_sel { 
#define UCHE_TRAP_BASE_HI               0xe84

#define A4XX_UCHE_INVALIDATE0		0xe8a

#define A4XX_UCHE_INVALIDATE1		0xe8b

#define A4XX_UCHE_CACHE_WAYS_VFD	0xe8c



/* VSC registers */

#define A4XX_VSC_SIZE_ADDRESS		0xc01

drivers/gpu/msm/adreno_a4xx.c

+3 −0
Original line number Diff line number Diff line
@@ -595,6 +595,9 @@ static void a4xx_start(struct adreno_device *adreno_dev) 
	/* Turn on the GPU busy counter and let it run free */

	memset(&adreno_dev->busy_data, 0, sizeof(adreno_dev->busy_data));



	/* Enable VFD to access most of the UCHE (7 ways out of 8) */

	kgsl_regwrite(device, A4XX_UCHE_CACHE_WAYS_VFD, 0x07);



	/* Disable L2 bypass to avoid UCHE out of bounds errors */

	kgsl_regwrite(device, UCHE_TRAP_BASE_LO, 0xffff0000);

	kgsl_regwrite(device, UCHE_TRAP_BASE_HI, 0xffff0000);