Loading arch/arm/boot/dts/qcom/msm8992.dtsi +37 −1 Original line number Diff line number Diff line Loading @@ -525,7 +525,43 @@ }; clock_cpu: qcom,cpu-clock-8992@f9015000 { compatible = "qcom,dummycc"; compatible = "qcom,cpu-clock-8992"; reg = <0xf9015000 0x1000>, <0xf9016000 0x1000>, <0xf9011000 0x1000>, <0xf900d000 0x1000>, <0xf900f000 0x1000>, <0xf9112000 0x1000>, <0xfc4b80b0 0x8>; reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux", "efuse"; vdd-a53-supply = <&apc0_vreg_corner>; vdd-a57-supply = <&apc1_vreg_corner>; vdd-cci-supply = <&apc0_vreg_corner>; vdd-dig-supply = <&pm8994_s2_corner_ao>; qcom,a53-speedbin0-v0 = < 0 0>, < 300000000 1>, < 384000000 2>, < 460800000 3>, < 600000000 4>, < 672000000 5>, < 787200000 6>; qcom,a57-speedbin0-v0 = < 0 0>, < 300000000 2>, < 384000000 3>; qcom,cci-speedbin0-v0 = < 0 0>, < 134400000 1>, < 300000000 4>, < 384000000 6>, < 556800000 8>, < 600000000 9>, < 729600000 9>, < 787200000 9>; clock-names = "xo_ao", "aux_clk"; clocks = <&clock_rpm clk_cxo_clk_src_ao>, <&clock_gcc clk_gpll0_ao>; #clock-cells = <1>; }; Loading Loading
arch/arm/boot/dts/qcom/msm8992.dtsi +37 −1 Original line number Diff line number Diff line Loading @@ -525,7 +525,43 @@ }; clock_cpu: qcom,cpu-clock-8992@f9015000 { compatible = "qcom,dummycc"; compatible = "qcom,cpu-clock-8992"; reg = <0xf9015000 0x1000>, <0xf9016000 0x1000>, <0xf9011000 0x1000>, <0xf900d000 0x1000>, <0xf900f000 0x1000>, <0xf9112000 0x1000>, <0xfc4b80b0 0x8>; reg-names = "c0_pll", "c1_pll", "cci_pll", "c0_mux", "c1_mux", "cci_mux", "efuse"; vdd-a53-supply = <&apc0_vreg_corner>; vdd-a57-supply = <&apc1_vreg_corner>; vdd-cci-supply = <&apc0_vreg_corner>; vdd-dig-supply = <&pm8994_s2_corner_ao>; qcom,a53-speedbin0-v0 = < 0 0>, < 300000000 1>, < 384000000 2>, < 460800000 3>, < 600000000 4>, < 672000000 5>, < 787200000 6>; qcom,a57-speedbin0-v0 = < 0 0>, < 300000000 2>, < 384000000 3>; qcom,cci-speedbin0-v0 = < 0 0>, < 134400000 1>, < 300000000 4>, < 384000000 6>, < 556800000 8>, < 600000000 9>, < 729600000 9>, < 787200000 9>; clock-names = "xo_ao", "aux_clk"; clocks = <&clock_rpm clk_cxo_clk_src_ao>, <&clock_gcc clk_gpll0_ao>; #clock-cells = <1>; }; Loading