Loading arch/arm/boot/dts/qcom/msmzirc-cc.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -279,6 +279,18 @@ qcom,key = "KHz"; qcom,rpm-peer = <&ce_clk>; }; qcedev_ce_clk: qcedev_ce_clk { compatible = "qcom,sw-vote-clk"; qcom,parent = <&ce_clk>; qcom,config-rate = <85710000>; }; qcrypto_ce_clk: qcrypto_ce_clk { compatible = "qcom,sw-vote-clk"; qcom,parent = <&ce_clk>; qcom,config-rate = <85710000>; }; }; &clock_gcc { Loading include/dt-bindings/clock/msm-clocks-zirc.h +4 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,10 @@ #define clk_qpic_a_clk &qpic_a_clk #define clk_ln_bb_clk &ln_bb_clk #define clk_cxo_dwc3_clk &cxo_dwc3_clk #define clk_ce_clk &ce_clk #define clk_ce_a_clk &ce_a_clk #define clk_qcedev_ce_clk &qcedev_ce_clk #define clk_qcrypto_ce_clk &qcrypto_ce_clk /* clock_gcc controlled clocks */ #define clk_gpll0 &gpll0 Loading Loading
arch/arm/boot/dts/qcom/msmzirc-cc.dtsi +12 −0 Original line number Diff line number Diff line Loading @@ -279,6 +279,18 @@ qcom,key = "KHz"; qcom,rpm-peer = <&ce_clk>; }; qcedev_ce_clk: qcedev_ce_clk { compatible = "qcom,sw-vote-clk"; qcom,parent = <&ce_clk>; qcom,config-rate = <85710000>; }; qcrypto_ce_clk: qcrypto_ce_clk { compatible = "qcom,sw-vote-clk"; qcom,parent = <&ce_clk>; qcom,config-rate = <85710000>; }; }; &clock_gcc { Loading
include/dt-bindings/clock/msm-clocks-zirc.h +4 −0 Original line number Diff line number Diff line Loading @@ -36,6 +36,10 @@ #define clk_qpic_a_clk &qpic_a_clk #define clk_ln_bb_clk &ln_bb_clk #define clk_cxo_dwc3_clk &cxo_dwc3_clk #define clk_ce_clk &ce_clk #define clk_ce_a_clk &ce_a_clk #define clk_qcedev_ce_clk &qcedev_ce_clk #define clk_qcrypto_ce_clk &qcrypto_ce_clk /* clock_gcc controlled clocks */ #define clk_gpll0 &gpll0 Loading