clk: qcom: clock-cpu-8994: Optimize frequency switches

1. PLL ping pong
MSM8994V2 has a 300MHz source for the cluster CPU clocks.
This allows the low power mode frequency to be sourced off
of the exclusive 300MHz source, while operational (DCVS)
frequencies can be sourced from the dedicated CPU PLLs.
This in turn allows frequency switching to be optimized;
the alternate PLL is simply reprogrammed and switched to,
without using an intermediate source.

2. Avoid mux switching for frequency multiples/factors
PLL ping pong invalidates the necessity for an intermediate
safe parent. Also, due to the intermediate divider between
the HFMUX and LFMUX and the divided versus undivided outputs
of the PLLs, certain frequencies may just be multiples or
factors of other frequencies. Switching between these should
not involve mux switches; just divider adjustments. Use
the try_get_rate feature of the generic mux code to achieve
this.

Change-Id: Idd45e944b308cc3c7ea14b1596b4c51e0718ed73
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>