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Commit 681aaf0c authored by Vikram Mulukutla's avatar Vikram Mulukutla
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clk: qcom: clock-pll: Conditionally fail round_rate if a pll is prepared



Some clock trees allow ping-ponging between PLLs in
order to optimize frequency switching. To allow
the mux round_rate logic to work, fail round_rate
if a PLL is already prepared, if a feature flag is
set.

Change-Id: I63bcc3bcc9967348b6986b47de529ccbfa78ad32
Signed-off-by: default avatarVikram Mulukutla <markivx@codeaurora.org>
parent fc903471
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+3 −0
Original line number Diff line number Diff line
@@ -496,6 +496,9 @@ static long variable_rate_pll_round_rate(struct clk *c, unsigned long rate)
	if (!pll->src_rate)
		return 0;

	if (pll->no_prepared_reconfig && c->prepare_count && c->rate != rate)
		return -EINVAL;

	if (rate < pll->min_rate)
		rate = pll->min_rate;
	if (rate > pll->max_rate)
+2 −0
Original line number Diff line number Diff line
@@ -121,6 +121,7 @@ static inline struct pll_vote_clk *to_pll_vote_clk(struct clk *c)
 * @masks: masks used for settings in config_reg
 * @vals: configuration values to be written to PLL registers
 * @freq_tbl: pll freq table
 * @no_prepared_reconfig: Fail round_rate if pll is prepared
 * @c: clk
 * @base: pointer to base address of ioremapped registers.
 */
@@ -148,6 +149,7 @@ struct pll_clk {
	unsigned long max_rate;

	bool inited;
	bool no_prepared_reconfig;

	struct clk c;
	void *const __iomem *base;