Loading arch/arm64/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -204,6 +204,25 @@ endmenu menu "Kernel Features" config ARM64_DCACHE_DISABLE bool "Disable CPU Data Caches" help Disable CPU data cache usage by setting the SCTLR[C] bit during kernel initialization. This will result in a considerable performance impact, but may be useful in certain situations. If you are not sure what to do, select 'N' here. config ARM64_ICACHE_DISABLE bool "Disable CPU Instruction Caches" help Disable CPU instruction cache usage by setting the SCTLR[I] bit during kernel initialization. This will result in a considerable performance impact, but may be useful in certain situations. If you are not sure what to do, select 'N' here. config ARM64_64K_PAGES bool "Enable 64KB pages support" help Loading arch/arm64/mm/proc.S +15 −2 Original line number Diff line number Diff line Loading @@ -235,5 +235,18 @@ ENDPROC(__cpu_setup) */ .type crval, #object crval: #ifdef CONFIG_ARM64_ICACHE_DISABLE #define CR_IBIT 0 #else #define CR_IBIT 0x1000 #endif #ifdef CONFIG_ARM64_DCACHE_DISABLE #define CR_CBIT 0 #else #define CR_CBIT 0x4 #endif .word 0x000802c2 // clear .word 0x0405d13d // set .word 0x0405c139 | CR_IBIT | CR_CBIT // set Loading
arch/arm64/Kconfig +19 −0 Original line number Diff line number Diff line Loading @@ -204,6 +204,25 @@ endmenu menu "Kernel Features" config ARM64_DCACHE_DISABLE bool "Disable CPU Data Caches" help Disable CPU data cache usage by setting the SCTLR[C] bit during kernel initialization. This will result in a considerable performance impact, but may be useful in certain situations. If you are not sure what to do, select 'N' here. config ARM64_ICACHE_DISABLE bool "Disable CPU Instruction Caches" help Disable CPU instruction cache usage by setting the SCTLR[I] bit during kernel initialization. This will result in a considerable performance impact, but may be useful in certain situations. If you are not sure what to do, select 'N' here. config ARM64_64K_PAGES bool "Enable 64KB pages support" help Loading
arch/arm64/mm/proc.S +15 −2 Original line number Diff line number Diff line Loading @@ -235,5 +235,18 @@ ENDPROC(__cpu_setup) */ .type crval, #object crval: #ifdef CONFIG_ARM64_ICACHE_DISABLE #define CR_IBIT 0 #else #define CR_IBIT 0x1000 #endif #ifdef CONFIG_ARM64_DCACHE_DISABLE #define CR_CBIT 0 #else #define CR_CBIT 0x4 #endif .word 0x000802c2 // clear .word 0x0405d13d // set .word 0x0405c139 | CR_IBIT | CR_CBIT // set