arm64: Add work around for Arm Cortex-A55 Erratum 1024718

Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to skip enabling the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected. There are some other cores suffering from this
errata, which could be added to the midr_list to trigger the work
around.

Change-Id: If8cf237afcf79af0c5707e7a471c3d18f1c88972
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: ckadabi@codeaurora.org
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: ece1397cbc89c51914fae1aec729539cfd8bd62b
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[isaacm@codeaurora.org: remove code that is not needed for
 having a way of expressing the list of CPUs that would
 be impacted by erratum 1024718.]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>