Commit a0ce5af2 authored Mar 26, 2018 by Suzuki K Poulose Committed by Isaac J. Manjarres May 30, 2018

arm64: Add work around for Arm Cortex-A55 Erratum 1024718



Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to skip enabling the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected. There are some other cores suffering from this
errata, which could be added to the midr_list to trigger the work
around.

Change-Id: If8cf237afcf79af0c5707e7a471c3d18f1c88972
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: ckadabi@codeaurora.org
Reviewed-by: Dave Martin <dave.martin@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Git-commit: ece1397cbc89c51914fae1aec729539cfd8bd62b
Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git


[isaacm@codeaurora.org: remove code that is not needed for
 having a way of expressing the list of CPUs that would
 be impacted by erratum 1024718.]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>

parent 7a6d8c2c

arch/arm64/kernel/cpufeature.c

+15 −1

Original line number	Original line	Diff line number	Diff line
	@@ -889,6 +889,20 @@ static inline void __cpu_enable_hw_dbm(void)
	isb();		isb();
	}		}

			static bool cpu_has_broken_dbm(void)
			{
			/* List of CPUs which have broken DBM support. */
			static const struct midr_range cpus[] = {
			#ifdef CONFIG_ARM64_ERRATUM_1024718
			// A55 r0p0 -r1p0
			GENERIC_MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),
			#endif
			{},
			};

			return is_midr_in_range_list(read_cpuid_id(), cpus);
			}

	static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)		static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
	{		{
	bool has_cpu_feature;		bool has_cpu_feature;
	@@ -897,7 +911,7 @@ static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
	has_cpu_feature = has_cpuid_feature(cap, SCOPE_LOCAL_CPU);		has_cpu_feature = has_cpuid_feature(cap, SCOPE_LOCAL_CPU);
	preempt_enable();		preempt_enable();

	return has_cpu_feature;		return has_cpu_feature && !cpu_has_broken_dbm();
	}		}

	static int cpu_enable_hw_dbm(void *entry)		static int cpu_enable_hw_dbm(void *entry)