Loading drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_100.h +24 −4 Original line number Diff line number Diff line Loading @@ -291,7 +291,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ Loading Loading @@ -339,7 +344,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ Loading Loading @@ -389,7 +399,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -439,7 +454,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ Loading drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_101.h +24 −4 Original line number Diff line number Diff line Loading @@ -291,7 +291,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ Loading Loading @@ -339,7 +344,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ Loading Loading @@ -389,7 +399,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -439,7 +454,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ Loading Loading
drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_100.h +24 −4 Original line number Diff line number Diff line Loading @@ -291,7 +291,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ Loading Loading @@ -339,7 +344,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ Loading Loading @@ -389,7 +399,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -439,7 +454,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ Loading
drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_101.h +24 −4 Original line number Diff line number Diff line Loading @@ -291,7 +291,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */ Loading Loading @@ -339,7 +344,12 @@ static struct cam_camnoc_specific .value = 0x1, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */ Loading Loading @@ -389,7 +399,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */ Loading Loading @@ -439,7 +454,12 @@ static struct cam_camnoc_specific .value = 0x0, }, .ubwc_ctl = { .enable = true, /* * Do not explicitly set ubwc config register. * Power on default values are taking care of required * register settings. */ .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */ Loading