Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit c9b08f98 authored by Pavan Kumar Chilamkurthi's avatar Pavan Kumar Chilamkurthi
Browse files

msm: camera: cpas: Do not explicitly set ubwc config registers 



Power on default register values are already having required
ubwc config bits set, no need to set the registers explicitly.

Change-Id: If76784efdab3d0aa61051f5c1dcd48999121b577
Signed-off-by: default avatarPavan Kumar Chilamkurthi <pchilamk@codeaurora.org>
parent 8ecd48cc

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_100.h

+24 −4
Original line number Diff line number Diff line
@@ -291,7 +291,12 @@ static struct cam_camnoc_specific 
			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
@@ -339,7 +344,12 @@ static struct cam_camnoc_specific 
			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
@@ -389,7 +399,12 @@ static struct cam_camnoc_specific 
			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
@@ -439,7 +454,12 @@ static struct cam_camnoc_specific 
			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */

drivers/media/platform/msm/camera/cam_cpas/cpas_top/cpastop_v175_101.h

+24 −4
Original line number Diff line number Diff line
@@ -291,7 +291,12 @@ static struct cam_camnoc_specific 
			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
@@ -339,7 +344,12 @@ static struct cam_camnoc_specific 
			.value = 0x1,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
@@ -389,7 +399,12 @@ static struct cam_camnoc_specific 
			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0xd08, /* SPECIFIC_IBL_RD_DECCTL_LOW */
@@ -439,7 +454,12 @@ static struct cam_camnoc_specific 
			.value = 0x0,

		},

		.ubwc_ctl = {

			.enable = true,

			/*

			 * Do not explicitly set ubwc config register.

			 * Power on default values are taking care of required

			 * register settings.

			 */

			.enable = false,

			.access_type = CAM_REG_TYPE_READ_WRITE,

			.masked_value = 0,

			.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */