Merge changes Ic1bdd9c6,I8b50eef7,I847242ed,I0ff00b0e,I18f4fb6f,I86bdd70f,I7ab96904 into msm-4.14 (cb7149ab) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/sde/sde_crtc.c

+126 −221

Original line number	Diff line number	Diff line
		@@ -38,15 +38,6 @@
		#include "sde_power_handle.h"
		#include "sde_core_perf.h"
		#include "sde_trace.h"
		#include <soc/qcom/scm.h>
		#include "soc/qcom/secure_buffer.h"

		/* defines for secure channel call */
		#define SEC_SID_CNT 2
		#define SEC_SID_MASK_0 0x80881
		#define SEC_SID_MASK_1 0x80C81
		#define MEM_PROTECT_SD_CTRL_SWITCH 0x18
		#define MDP_DEVICE_ID 0x1A

		#define SDE_PSTATES_MAX (SDE_STAGE_MAX * 4)
		#define SDE_MULTIRECT_PLANE_MAX (SDE_STAGE_MAX * 2)
		@@ -1793,8 +1784,9 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		struct drm_plane *plane;
		struct drm_encoder *encoder;
		struct sde_crtc *sde_crtc;
		struct sde_crtc_state *cstate;
		struct sde_crtc_smmu_state_data *smmu_state;
		struct sde_kms *sde_kms;
		struct sde_mdss_cfg *catalog;
		struct sde_kms_smmu_state_data *smmu_state;
		uint32_t translation_mode = 0, secure_level;
		int ops = 0;
		bool post_commit = false;
		@@ -1804,10 +1796,14 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		return -EINVAL;
		}

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms)
		return -EINVAL;

		smmu_state = &sde_kms->smmu_state;
		sde_crtc = to_sde_crtc(crtc);
		cstate = to_sde_crtc_state(crtc->state);
		smmu_state = &sde_crtc->smmu_state;
		secure_level = sde_crtc_get_secure_level(crtc, crtc->state);
		catalog = sde_kms->catalog;

		SDE_DEBUG("crtc%d, secure_level%d old_valid_fb%d\n",
		crtc->base.id, secure_level, old_valid_fb);
		@@ -1848,6 +1844,8 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		break;
		}

		mutex_lock(&sde_kms->secure_transition_lock);

		switch (translation_mode) {
		case SDE_DRM_FB_SEC_DIR_TRANS:
		/* secure display usecase */
		@@ -1855,18 +1853,22 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		(secure_level == SDE_DRM_SEC_ONLY)) {
		smmu_state->state = DETACH_ALL_REQ;
		smmu_state->transition_type = PRE_COMMIT;
		ops \|= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE;
		ops \|= SDE_KMS_OPS_SECURE_STATE_CHANGE;
		if (old_valid_fb) {
		ops \|= (SDE_KMS_OPS_WAIT_FOR_TX_DONE \|
		SDE_KMS_OPS_CLEANUP_PLANE_FB);
		}
		if (catalog->sui_misr_supported)
		smmu_state->sui_misr_state =
		SUI_MISR_ENABLE_REQ;
		/* secure camera usecase */
		} else if (smmu_state->state == ATTACHED) {
		smmu_state->state = DETACH_SEC_REQ;
		smmu_state->transition_type = PRE_COMMIT;
		ops \|= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE;
		ops \|= SDE_KMS_OPS_SECURE_STATE_CHANGE;
		}
		break;

		case SDE_DRM_FB_SEC:
		case SDE_DRM_FB_NON_SEC:
		if ((smmu_state->state == DETACHED_SEC) \|\|
		@@ -1874,7 +1876,7 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		smmu_state->state = ATTACH_SEC_REQ;
		smmu_state->transition_type = post_commit ?
		POST_COMMIT : PRE_COMMIT;
		ops \|= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE;
		ops \|= SDE_KMS_OPS_SECURE_STATE_CHANGE;
		if (old_valid_fb)
		ops \|= SDE_KMS_OPS_WAIT_FOR_TX_DONE;
		} else if ((smmu_state->state == DETACHED) \|\|
		@@ -1882,16 +1884,19 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		smmu_state->state = ATTACH_ALL_REQ;
		smmu_state->transition_type = post_commit ?
		POST_COMMIT : PRE_COMMIT;
		ops \|= SDE_KMS_OPS_CRTC_SECURE_STATE_CHANGE;
		ops \|= SDE_KMS_OPS_SECURE_STATE_CHANGE;
		if (old_valid_fb)
		ops \|= (SDE_KMS_OPS_WAIT_FOR_TX_DONE \|
		SDE_KMS_OPS_CLEANUP_PLANE_FB);
		if (catalog->sui_misr_supported)
		smmu_state->sui_misr_state =
		SUI_MISR_DISABLE_REQ;
		}
		break;

		default:
		SDE_ERROR("invalid plane fb_mode:%d\n", translation_mode);
		ops = 0;
		return -EINVAL;
		ops = -EINVAL;
		}

		SDE_DEBUG("SMMU State:%d, type:%d ops:%x\n", smmu_state->state,
		@@ -1901,55 +1906,10 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc,
		SDE_EVT32(DRMID(crtc), secure_level, translation_mode,
		smmu_state->state, smmu_state->transition_type,
		ops, old_valid_fb, SDE_EVTLOG_FUNC_EXIT);
		return ops;
		}

		/**
		* _sde_crtc_scm_call - makes secure channel call to switch the VMIDs
		* @vimd: switch the stage 2 translation to this VMID.
		*/
		static int _sde_crtc_scm_call(int vmid)
		{
		struct scm_desc desc = {0};
		uint32_t num_sids;
		uint32_t *sec_sid;
		uint32_t mem_protect_sd_ctrl_id = MEM_PROTECT_SD_CTRL_SWITCH;
		int ret = 0;

		/* This info should be queried from catalog */
		num_sids = SEC_SID_CNT;
		sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
		if (!sec_sid)
		return -ENOMEM;

		/**
		* derive this info from device tree/catalog, this is combination of
		* smr mask and SID for secure
		*/
		sec_sid[0] = SEC_SID_MASK_0;
		sec_sid[1] = SEC_SID_MASK_1;
		dmac_flush_range(sec_sid, sec_sid + num_sids);

		SDE_DEBUG("calling scm_call for vmid %d", vmid);
		mutex_unlock(&sde_kms->secure_transition_lock);

		desc.arginfo = SCM_ARGS(4, SCM_VAL, SCM_RW, SCM_VAL, SCM_VAL);
		desc.args[0] = MDP_DEVICE_ID;
		desc.args[1] = SCM_BUFFER_PHYS(sec_sid);
		desc.args[2] = sizeof(uint32_t) * num_sids;
		desc.args[3] = vmid;

		ret = scm_call2(SCM_SIP_FNID(SCM_SVC_MP,
		mem_protect_sd_ctrl_id), &desc);
		if (ret) {
		SDE_ERROR("Error:scm_call2, vmid (%lld): ret%d\n",
		desc.args[3], ret);
		}
		SDE_EVT32(mem_protect_sd_ctrl_id,
		desc.args[0], desc.args[3], num_sids,
		sec_sid[0], sec_sid[1], ret);

		kfree(sec_sid);
		return ret;
		return ops;
		}

		/**
		@@ -2022,130 +1982,6 @@ void sde_crtc_timeline_status(struct drm_crtc *crtc)
		sde_fence_timeline_status(&sde_crtc->output_fence, &crtc->base);
		}

		/**
		* sde_crtc_secure_ctrl - Initiates the operations to switch between secure
		* and non-secure mode
		* @crtc: Pointer to crtc
		* @post_commit: if this operation is triggered after commit
		*/
		int sde_crtc_secure_ctrl(struct drm_crtc *crtc, bool post_commit)
		{
		struct sde_crtc *sde_crtc;
		struct sde_crtc_state *cstate;
		struct sde_kms *sde_kms;
		struct sde_crtc_smmu_state_data *smmu_state;
		int ret = 0;
		int old_smmu_state;

		if (!crtc \|\| !crtc->state) {
		SDE_ERROR("invalid crtc\n");
		return -EINVAL;
		}

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms) {
		SDE_ERROR("invalid kms\n");
		return -EINVAL;
		}

		sde_crtc = to_sde_crtc(crtc);
		cstate = to_sde_crtc_state(crtc->state);
		smmu_state = &sde_crtc->smmu_state;
		old_smmu_state = smmu_state->state;

		SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
		post_commit, SDE_EVTLOG_FUNC_ENTRY);

		if ((!smmu_state->transition_type) \|\|
		((smmu_state->transition_type == POST_COMMIT) && !post_commit))
		/* Bail out */
		return 0;

		/* Secure UI use case enable */
		switch (smmu_state->state) {
		case DETACH_ALL_REQ:
		/* detach_all_contexts */
		ret = sde_kms_mmu_detach(sde_kms, false);
		if (ret) {
		SDE_ERROR("crtc: %d, failed to detach %d\n",
		crtc->base.id, ret);
		goto error;
		}

		ret = _sde_crtc_scm_call(VMID_CP_SEC_DISPLAY);
		if (ret)
		goto error;

		smmu_state->state = DETACHED;
		break;
		/* Secure UI use case disable */
		case ATTACH_ALL_REQ:
		ret = _sde_crtc_scm_call(VMID_CP_PIXEL);
		if (ret)
		goto error;

		/* attach_all_contexts */
		ret = sde_kms_mmu_attach(sde_kms, false);
		if (ret) {
		SDE_ERROR("crtc: %d, failed to attach %d\n",
		crtc->base.id,
		ret);
		goto error;
		}

		smmu_state->state = ATTACHED;

		break;
		/* Secure preview enable */
		case DETACH_SEC_REQ:
		/* detach secure_context */
		ret = sde_kms_mmu_detach(sde_kms, true);
		if (ret) {
		SDE_ERROR("crtc: %d, failed to detach %d\n",
		crtc->base.id,
		ret);
		goto error;
		}

		smmu_state->state = DETACHED_SEC;
		ret = _sde_crtc_scm_call(VMID_CP_CAMERA_PREVIEW);
		if (ret)
		goto error;

		break;

		/* Secure preview disable */
		case ATTACH_SEC_REQ:
		ret = _sde_crtc_scm_call(VMID_CP_PIXEL);
		if (ret)
		goto error;

		ret = sde_kms_mmu_attach(sde_kms, true);
		if (ret) {
		SDE_ERROR("crtc: %d, failed to attach %d\n",
		crtc->base.id,
		ret);
		goto error;
		}
		smmu_state->state = ATTACHED;
		break;
		default:
		break;
		}

		SDE_DEBUG("crtc: %d, old_state %d new_state %d\n", crtc->base.id,
		old_smmu_state,
		smmu_state->state);
		smmu_state->transition_type = NONE;

		error:
		smmu_state->transition_error = ret ? true : false;
		SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
		smmu_state->transition_error, ret,
		SDE_EVTLOG_FUNC_EXIT);
		return ret;
		}

		static int _sde_validate_hw_resources(struct sde_crtc *sde_crtc)
		{
		int i;
		@@ -2581,7 +2417,6 @@ void sde_crtc_complete_commit(struct drm_crtc *crtc,
		struct drm_crtc_state *old_state)
		{
		struct sde_crtc *sde_crtc;
		struct sde_crtc_smmu_state_data *smmu_state;

		if (!crtc \|\| !crtc->state) {
		SDE_ERROR("invalid crtc\n");
		@@ -2590,13 +2425,8 @@ void sde_crtc_complete_commit(struct drm_crtc *crtc,

		sde_crtc = to_sde_crtc(crtc);
		SDE_EVT32_VERBOSE(DRMID(crtc));
		smmu_state = &sde_crtc->smmu_state;

		sde_core_perf_crtc_update(crtc, 0, false);

		/* complete secure transitions if any */
		if (smmu_state->transition_type == POST_COMMIT)
		sde_crtc_secure_ctrl(crtc, true);
		}

		/**
		@@ -3204,7 +3034,7 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
		struct drm_encoder *encoder;
		struct drm_device *dev;
		unsigned long flags;
		struct sde_crtc_smmu_state_data *smmu_state;
		struct sde_kms *sde_kms;

		if (!crtc) {
		SDE_ERROR("invalid crtc\n");
		@@ -3222,11 +3052,14 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
		return;
		}

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms)
		return;

		SDE_DEBUG("crtc%d\n", crtc->base.id);

		sde_crtc = to_sde_crtc(crtc);
		dev = crtc->dev;
		smmu_state = &sde_crtc->smmu_state;

		if (!sde_crtc->num_mixers) {
		_sde_crtc_setup_mixers(crtc);
		@@ -3269,14 +3102,11 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,

		/*
		* Since CP properties use AXI buffer to program the
		* HW, check if context bank is in attached
		* state,
		* HW, check if context bank is in attached state,
		* apply color processing properties only if
		* smmu state is attached,
		*/
		if ((smmu_state->state != DETACHED) &&
		(smmu_state->state != DETACH_ALL_REQ) &&
		sde_crtc->enabled)
		if (!sde_kms_is_secure_session_inprogress(sde_kms))
		sde_cp_crtc_apply_properties(crtc);

		/*
		@@ -3299,6 +3129,7 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
		struct msm_drm_thread *event_thread;
		unsigned long flags;
		struct sde_crtc_state *cstate;
		struct sde_kms *sde_kms;
		int idle_time = 0;

		if (!crtc \|\| !crtc->dev \|\| !crtc->dev->dev_private) {
		@@ -3317,6 +3148,12 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
		return;
		}

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms) {
		SDE_ERROR("invalid kms\n");
		return;
		}

		SDE_DEBUG("crtc%d\n", crtc->base.id);

		sde_crtc = to_sde_crtc(crtc);
		@@ -3390,7 +3227,7 @@ static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
		* everything" call below.
		*/
		drm_atomic_crtc_for_each_plane(plane, crtc) {
		if (sde_crtc->smmu_state.transition_error)
		if (sde_kms->smmu_state.transition_error)
		sde_plane_set_error(plane, true);
		sde_plane_flush(plane);
		}
		@@ -4576,10 +4413,12 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
		struct drm_crtc_state *state, struct plane_state pstates[],
		int cnt)
		{
		struct drm_plane *plane;
		struct drm_encoder *encoder;
		struct sde_crtc_state *cstate;
		struct sde_crtc *sde_crtc;
		struct sde_crtc_smmu_state_data *smmu_state;
		struct sde_kms *sde_kms;
		struct sde_kms_smmu_state_data *smmu_state;
		uint32_t secure;
		uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
		int encoder_cnt = 0, i;
		@@ -4591,6 +4430,12 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
		return -EINVAL;
		}

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms) {
		SDE_ERROR("invalid kms\n");
		return -EINVAL;
		}

		cstate = to_sde_crtc_state(state);

		secure = sde_crtc_get_property(cstate, CRTC_PROP_SECURITY_LEVEL);
		@@ -4614,8 +4459,25 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
		return -EINVAL;
		}

		/* only one blending stage is allowed in sec_crtc */
		/*
		* - only one blending stage is allowed in sec_crtc
		* - validate if pipe is allowed for sec-ui updates
		*/
		for (i = 1; i < cnt; i++) {
		if (!pstates[i].drm_pstate
		\|\| !pstates[i].drm_pstate->plane) {
		SDE_ERROR("crtc%d: invalid pstate at i:%d\n",
		crtc->base.id, i);
		return -EINVAL;
		}
		plane = pstates[i].drm_pstate->plane;

		if (!sde_plane_is_sec_ui_allowed(plane)) {
		SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",
		crtc->base.id, plane->base.id);
		return -EINVAL;
		}

		if (pstates[i].stage != pstates[i-1].stage) {
		SDE_ERROR(
		"crtc%d: invalid blend stages %d:%d, %d:%d\n",
		@@ -4652,7 +4514,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc,
		}

		sde_crtc = to_sde_crtc(crtc);
		smmu_state = &sde_crtc->smmu_state;
		smmu_state = &sde_kms->smmu_state;
		/*
		* In video mode check for null commit before transition
		* from secure to non secure and vice versa
		@@ -5505,6 +5367,46 @@ int sde_crtc_helper_reset_custom_properties(struct drm_crtc *crtc,
		return 0;
		}

		void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count)
		{
		struct sde_kms *sde_kms;
		struct sde_crtc *sde_crtc;
		struct sde_crtc_mixer *m;
		int i;

		if (!crtc) {
		SDE_ERROR("invalid argument\n");
		return;
		}
		sde_crtc = to_sde_crtc(crtc);

		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms) {
		SDE_ERROR("invalid sde_kms\n");
		return;
		}

		mutex_lock(&sde_crtc->crtc_lock);
		if (sde_kms_is_secure_session_inprogress(sde_kms)) {
		SDE_DEBUG("crtc:%d misr enable/disable not allowed\n",
		DRMID(crtc));
		mutex_unlock(&sde_crtc->crtc_lock);
		return;
		}

		sde_crtc->misr_enable = enable;
		sde_crtc->misr_frame_count = frame_count;
		for (i = 0; i < sde_crtc->num_mixers; ++i) {
		sde_crtc->misr_data[i] = 0;
		m = &sde_crtc->mixers[i];
		if (!m->hw_lm \|\| !m->hw_lm->ops.setup_misr)
		continue;

		m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
		}
		mutex_unlock(&sde_crtc->crtc_lock);
		}

		#ifdef CONFIG_DEBUG_FS
		static int _sde_debugfs_status_show(struct seq_file s, void data)
		{
		@@ -5653,9 +5555,9 @@ static int _sde_debugfs_status_open(struct inode inode, struct file file)
		static ssize_t _sde_crtc_misr_setup(struct file *file,
		const char __user user_buf, size_t count, loff_t ppos)
		{
		struct drm_crtc *crtc;
		struct sde_crtc *sde_crtc;
		struct sde_crtc_mixer *m;
		int i = 0, rc;
		int rc;
		char buf[MISR_BUFF_SIZE + 1];
		u32 frame_count, enable;
		size_t buff_copy;
		@@ -5664,6 +5566,8 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
		return -EINVAL;

		sde_crtc = file->private_data;
		crtc = &sde_crtc->base;

		buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
		if (copy_from_user(buf, user_buf, buff_copy)) {
		SDE_ERROR("buffer copy failed\n");
		@@ -5679,18 +5583,7 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
		if (rc)
		return rc;

		mutex_lock(&sde_crtc->crtc_lock);
		sde_crtc->misr_enable = enable;
		sde_crtc->misr_frame_count = frame_count;
		for (i = 0; i < sde_crtc->num_mixers; ++i) {
		sde_crtc->misr_data[i] = 0;
		m = &sde_crtc->mixers[i];
		if (!m->hw_lm \|\| !m->hw_lm->ops.setup_misr)
		continue;

		m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
		}
		mutex_unlock(&sde_crtc->crtc_lock);
		sde_crtc_misr_setup(crtc, enable, frame_count);
		_sde_crtc_power_enable(sde_crtc, false);

		return count;
		@@ -5699,7 +5592,9 @@ static ssize_t _sde_crtc_misr_setup(struct file *file,
		static ssize_t _sde_crtc_misr_read(struct file *file,
		char __user user_buff, size_t count, loff_t ppos)
		{
		struct drm_crtc *crtc;
		struct sde_crtc *sde_crtc;
		struct sde_kms *sde_kms;
		struct sde_crtc_mixer *m;
		int i = 0, rc;
		u32 misr_status;
		@@ -5713,11 +5608,21 @@ static ssize_t _sde_crtc_misr_read(struct file *file,
		return -EINVAL;

		sde_crtc = file->private_data;
		crtc = &sde_crtc->base;
		sde_kms = _sde_crtc_get_kms(crtc);
		if (!sde_kms)
		return -EINVAL;

		rc = _sde_crtc_power_enable(sde_crtc, true);
		if (rc)
		return rc;

		mutex_lock(&sde_crtc->crtc_lock);
		if (sde_kms_is_secure_session_inprogress(sde_kms)) {
		SDE_DEBUG("crtc:%d misr read not allowed\n", DRMID(crtc));
		goto end;
		}

		if (!sde_crtc->misr_enable) {
		len += snprintf(buf + len, MISR_BUFF_SIZE - len,
		"disabled\n");

drivers/gpu/drm/msm/sde/sde_crtc.h

+8 −46

Original line number	Diff line number	Diff line
		@@ -47,50 +47,6 @@ enum sde_crtc_client_type {
		RT_RSC_CLIENT,
		};

		/**
		* enum sde_crtc_smmu_state: smmu state
		* @ATTACHED: all the context banks are attached.
		* @DETACHED: all the context banks are detached.
		* @DETACHED_SEC: secure context bank is detached.
		* @ATTACH_ALL_REQ: transient state of attaching context banks.
		* @DETACH_ALL_REQ: transient state of detaching context banks.
		* @DETACH_SEC_REQ: tranisent state of secure context bank is detached
		* @ATTACH_SEC_REQ: transient state of attaching secure context bank.
		*/
		enum sde_crtc_smmu_state {
		ATTACHED = 0,
		DETACHED,
		DETACHED_SEC,
		ATTACH_ALL_REQ,
		DETACH_ALL_REQ,
		DETACH_SEC_REQ,
		ATTACH_SEC_REQ,
		};

		/**
		* enum sde_crtc_smmu_state_transition_type: state transition type
		* @NONE: no pending state transitions
		* @PRE_COMMIT: state transitions should be done before processing the commit
		* @POST_COMMIT: state transitions to be done after processing the commit.
		*/
		enum sde_crtc_smmu_state_transition_type {
		NONE,
		PRE_COMMIT,
		POST_COMMIT
		};

		/**
		* struct sde_crtc_smmu_state_data: stores the smmu state and transition type
		* @state: current state of smmu context banks
		* @transition_type: transition request type
		* @transition_error: whether there is error while transitioning the state
		*/
		struct sde_crtc_smmu_state_data {
		uint32_t state;
		uint32_t transition_type;
		uint32_t transition_error;
		};

		/**
		* @connectors : Currently associated drm connectors for retire event
		* @num_connectors: Number of associated drm connectors for retire event
		@@ -296,8 +252,6 @@ struct sde_crtc {
		struct mutex rp_lock;
		struct list_head rp_head;

		struct sde_crtc_smmu_state_data smmu_state;

		/* blob for histogram data */
		struct drm_property_blob *hist_blob;
		};
		@@ -794,4 +748,12 @@ void sde_crtc_update_cont_splash_mixer_settings(
		*/
		uint64_t sde_crtc_get_sbuf_clk(struct drm_crtc_state *state);

		/**
		* sde_crtc_misr_setup - to configure and enable/disable MISR
		* @crtc: Pointer to drm crtc structure
		* @enable: boolean to indicate enable/disable misr
		* @frame_count: frame_count to be configured
		*/
		void sde_crtc_misr_setup(struct drm_crtc *crtc, bool enable, u32 frame_count);

		#endif /* _SDE_CRTC_H_ */

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+10 −0

Original line number	Diff line number	Diff line
		@@ -3554,6 +3554,16 @@ static int _sde_hardware_post_caps(struct sde_mdss_cfg *sde_cfg,
		max_vert_deci = max(max_vert_deci,
		sde_cfg->sspp[i].sblk->maxvdeciexp);
		}

		/*
		* set sec-ui blocked SSPP feature flag based on blocked
		* xin-mask if sec-ui-misr feature is enabled;
		*/
		if (sde_cfg->sui_misr_supported
		&& (sde_cfg->sui_block_xin_mask
		& BIT(sde_cfg->sspp[i].xin_id)))
		set_bit(SDE_SSPP_BLOCK_SEC_UI,
		&sde_cfg->sspp[i].features);
		}

		/* this should be updated based on HW rev in future */

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -149,6 +149,8 @@ enum {
		* @SDE_SSPP_INVERSE_PMA Alpha unmultiply (PMA) support
		* @SDE_SSPP_DGM_INVERSE_PMA Alpha unmultiply (PMA) support in DGM block
		* @SDE_SSPP_DGM_CSC Support of color space conversion in DGM block
		* @SDE_SSPP_SEC_UI_ALLOWED Allows secure-ui layers
		* @SDE_SSPP_BLOCK_SEC_UI Blocks secure-ui layers
		* @SDE_SSPP_MAX maximum value
		*/
		enum {
		@@ -179,6 +181,8 @@ enum {
		SDE_SSPP_INVERSE_PMA,
		SDE_SSPP_DGM_INVERSE_PMA,
		SDE_SSPP_DGM_CSC,
		SDE_SSPP_SEC_UI_ALLOWED,
		SDE_SSPP_BLOCK_SEC_UI,
		SDE_SSPP_MAX
		};

		@@ -1033,6 +1037,9 @@ struct sde_perf_cfg {
		* @macrotile_mode UBWC parameter for macro tile channel distribution
		* @pipe_order_type indicate if it is required to specify pipe order
		* @delay_prg_fetch_start indicates if throttling the fetch start is required
		* @sui_misr_supported indicate if secure-ui-misr is supported
		* @sui_block_xin_mask mask of all the xin-clients to be blocked during
		* secure-ui when secure-ui-misr feature is supported
		*/
		struct sde_mdss_cfg {
		u32 hwversion;
		@@ -1068,6 +1075,9 @@ struct sde_mdss_cfg {
		u32 pipe_order_type;
		bool delay_prg_fetch_start;

		bool sui_misr_supported;
		u32 sui_block_xin_mask;

		bool has_hdr;
		u32 mdss_count;
		struct sde_mdss_base_cfg mdss[MAX_BLOCKS];

drivers/gpu/drm/msm/sde/sde_kms.c

+308 −3

File changed.

Preview size limit exceeded, changes collapsed.