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Commit 7a1cf3ae authored by Alexander Beykun's avatar Alexander Beykun
Browse files

drm/msm/sde: add explicit pipe priority support 



Add support for HW that doesn`t have implicit priority order
and requires pipe order to be configured for a given pair of pipes.

Change-Id: I683d7454cccabb4957133ccaa05e448b6feeac8f
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 743dc39b

Documentation/devicetree/bindings/display/msm/sde.txt

+5 −0
Original line number Diff line number Diff line
@@ -409,6 +409,10 @@ Optional properties: 
                                for the ctl block. Possible values:

				"primary" - preferred for primary display

				"none" - no preference on display

- qcom,sde-pipe-order-version:	A u32 property to indicate version of pipe

				ordering block

				0: lower priority pipe has to be on the left for a given pair of pipes.

				1: priority have to be explicitly configured for a given pair of pipes.



Bus Scaling Subnodes:

- qcom,sde-reg-bus:		Property to provide Bus scaling for register access for
@@ -558,6 +562,7 @@ Example: 
    qcom,sde-smart-panel-align-mode = <0xd>;

    qcom,sde-panic-per-pipe;

    qcom,sde-has-src-split;

    qcom,sde-pipe-order-version = <0x1>;

    qcom,sde-has-dim-layer;

    qcom,sde-sspp-src-size = <0x100>;

    qcom,sde-mixer-size = <0x100>;

drivers/gpu/drm/msm/sde/sde_crtc.c

+16 −1
Original line number Diff line number Diff line
@@ -4654,6 +4654,7 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
	struct sde_crtc *sde_crtc;

	struct plane_state *pstates = NULL;

	struct sde_crtc_state *cstate;

	struct sde_kms *kms;



	const struct drm_plane_state *pstate;

	struct drm_plane *plane;
@@ -4671,6 +4672,13 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
		return -EINVAL;

	}



	kms = _sde_crtc_get_kms(crtc);



	if (!kms || !kms->catalog) {

		SDE_ERROR("invalid parameters\n");

		return -EINVAL;

	}



	sde_crtc = to_sde_crtc(crtc);

	cstate = to_sde_crtc_state(state);
@@ -4742,6 +4750,7 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
			continue;



		pstates[cnt].sde_pstate = to_sde_plane_state(pstate);

		pstates[cnt].sde_pstate->pipe_order_flags = 0x0;

		pstates[cnt].drm_pstate = pstate;

		pstates[cnt].stage = sde_plane_get_property(

				pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
@@ -4912,6 +4921,7 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
		if (right_rect.x < left_rect.x) {

			swap(left_pid, right_pid);

			swap(left_rect, right_rect);

			swap(prv_pstate, cur_pstate);

		}



		/**
@@ -4921,7 +4931,8 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
		 * - planes in source split must be contiguous in width

		 * - planes in source split must have same dest yoff and height

		 */

		if (right_pid < left_pid) {

		if ((right_pid < left_pid) &&

			!kms->catalog->pipe_order_type) {

			SDE_ERROR(

				"invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",

				stage, left_pid, right_pid);
@@ -4943,6 +4954,10 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
			rc = -EINVAL;

			goto end;

		}



		if (kms->catalog->pipe_order_type)

			cur_pstate->sde_pstate->pipe_order_flags =

				SDE_SSPP_RIGHT;

	}



	rc = _sde_crtc_check_rois(crtc, state);

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+5 −0
Original line number Diff line number Diff line
@@ -155,6 +155,7 @@ enum sde_prop { 
	SMART_PANEL_ALIGN_MODE,

	MACROTILE_MODE,

	UBWC_BW_CALC_VERSION,

	PIPE_ORDER_VERSION,

	SDE_PROP_MAX,

};
@@ -425,6 +426,8 @@ static struct sde_prop_type sde_prop[] = { 
	{MACROTILE_MODE, "qcom,sde-macrotile-mode", false, PROP_TYPE_U32},

	{UBWC_BW_CALC_VERSION, "qcom,sde-ubwc-bw-calc-version", false,

			PROP_TYPE_U32},

	{PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false,

			PROP_TYPE_U32},

};



static struct sde_prop_type sde_perf_prop[] = {
@@ -2951,6 +2954,8 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	cfg->has_src_split = PROP_VALUE_ACCESS(prop_value, SRC_SPLIT, 0);

	cfg->has_dim_layer = PROP_VALUE_ACCESS(prop_value, DIM_LAYER, 0);

	cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0);

	cfg->pipe_order_type = PROP_VALUE_ACCESS(prop_value,

		PIPE_ORDER_VERSION, 0);

end:

	kfree(prop_value);

	return rc;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1003,6 +1003,7 @@ struct sde_perf_cfg { 
 * @vbif_qos_nlvl      number of vbif QoS priority level

 * @ts_prefill_rev     prefill traffic shaper feature revision

 * @macrotile_mode     UBWC parameter for macro tile channel distribution

 * @pipe_order_type    indicate if it is required to specify pipe order

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1028,6 +1029,7 @@ struct sde_mdss_cfg { 
	u32 vbif_qos_nlvl;

	u32 ts_prefill_rev;

	u32 macrotile_mode;

	u32 pipe_order_type;



	bool has_hdr;

	u32 mdss_count;

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+5 −1
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ 
#define MDSS_MDP_OP_IGC_EN                 BIT(16)

#define MDSS_MDP_OP_FLIP_UD                BIT(14)

#define MDSS_MDP_OP_FLIP_LR                BIT(13)

#define MDSS_MDP_OP_SPLIT_ORDER            BIT(4)

#define MDSS_MDP_OP_BWC_EN                 BIT(0)

#define MDSS_MDP_OP_PE_OVERRIDE            BIT(31)

#define MDSS_MDP_OP_BWC_LOSSLESS           (0 << 1)
@@ -286,12 +287,15 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, 
	c = &ctx->hw;

	opmode = SDE_REG_READ(c, op_mode_off + idx);

	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |

			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);

			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE |

			MDSS_MDP_OP_SPLIT_ORDER);



	if (flags & SDE_SSPP_FLIP_LR)

		opmode |= MDSS_MDP_OP_FLIP_LR;

	if (flags & SDE_SSPP_FLIP_UD)

		opmode |= MDSS_MDP_OP_FLIP_UD;

	if ((flags & SDE_SSPP_RIGHT) && ctx->catalog->pipe_order_type)

		opmode |= MDSS_MDP_OP_SPLIT_ORDER;



	chroma_samp = fmt->chroma_sample;

	if (flags & SDE_SSPP_SOURCE_ROTATED_90) {