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Commit 034d5c65 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add video node for sdm855"

parents 1fe3424e bbbce2f5

Documentation/devicetree/bindings/media/video/msm-vidc.txt

+1 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ Venus 
Required properties:

- compatible : one of:

	- "qcom,msm-vidc"

        - "qcom,sdm855-vidc" : Invokes driver specific data for SDM855.

        - "qcom,sdm845-vidc" : Invokes driver specific data for SDM845.

        - "qcom,sdm670-vidc" : Invokes driver specific data for SDM670.

arch/arm64/boot/dts/qcom/sdm855-vidc.dtsi

0 → 100644
+124 −0
Original line number Diff line number Diff line 
/* Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/clock/qcom,videocc-sdm855.h>



&soc {

	msm_vidc: qcom,vidc@aa00000 {

		compatible = "qcom,msm-vidc", "qcom,sdm855-vidc";

		status = "disabled";

		reg = <0xaa00000 0x200000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



		/* Supply */

		iris-ctl-supply = <&mvsc_gdsc>;

		vcodec-supply = <&mvs0_gdsc>;

		cvp-supply = <&mvs1_gdsc>;



		/* Clocks */

		clock-names = "core_clk", "iface_clk",

			"vcodec_clk", "cvp_clk", "gcc_video_axi0",

			"gcc_video_axi1", "gcc_video_axic";

		clocks = <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>,

			<&clock_videocc VIDEO_CC_IRIS_AHB_CLK>,

			<&clock_videocc VIDEO_CC_MVS0_CORE_CLK>,

			<&clock_videocc VIDEO_CC_MVS1_CORE_CLK>,

			<&clock_gcc GCC_VIDEO_AXI0_CLK>,

			<&clock_gcc GCC_VIDEO_AXI1_CLK>,

			<&clock_gcc GCC_VIDEO_AXIC_CLK>;

		qcom,proxy-clock-names = "core_clk", "iface_clk",

			"vcodec_clk", "cvp_clk", "gcc_video_axi0",

			"gcc_video_axi1", "gcc_video_axic";

		qcom,clock-configs = <0x1 0x0 0x1 0x1 0x0 0x0 0x0>;

		qcom,allowed-clock-rates = <200000000 225000000

			300000000 365000000 432000000 480000000>;



		/* Buses */

		bus_cnoc {

			compatible = "qcom,msm-vidc,bus";

			label = "cnoc";

			qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;

			qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;

			qcom,bus-governor = "performance";

			qcom,bus-range-kbps = <1000 1000>;

		};



		venus_bus_ddr {

			compatible = "qcom,msm-vidc,bus";

			label = "venus-ddr";

			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;

			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;

			qcom,bus-governor = "performance";

			qcom,bus-range-kbps = <1000 100000000>;

		};

		arm9_bus_ddr {

			compatible = "qcom,msm-vidc,bus";

			label = "venus-arm9-ddr";

			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;

			qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;

			qcom,bus-governor = "performance";

			qcom,bus-range-kbps = <1000 1000>;

		};

		venus_bus_llcc {

			compatible = "qcom,msm-vidc,bus";

			label = "venus-llcc";

			qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;

			qcom,bus-slave = <MSM_BUS_SLAVE_LLCC>;

			qcom,bus-governor = "performance";

			qcom,bus-range-kbps = <1000 100000000>;

		};



		/* MMUs */

		non_secure_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";

			iommus =

				<&apps_smmu 0x1300 0x20>,

				<&apps_smmu 0x1340 0x0>;

			buffer-types = <0xfff>;

			virtual-addr-pool = <0x70800000 0x6f800000>;

		};



		secure_bitstream_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus =

				<&apps_smmu 0x1301 0x4>;

			buffer-types = <0x241>;

			virtual-addr-pool = <0x4b000000 0x25800000>;

			qcom,secure-context-bank;

		};



		secure_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus =

				<&apps_smmu 0x1303 0x20>;

			buffer-types = <0x106>;

			virtual-addr-pool = <0x25800000 0x25800000>;

			qcom,secure-context-bank;

		};



		secure_non_pixel_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus =

				<&apps_smmu 0x1304 0x20>,

				<&apps_smmu 0x1344 0x0>;

			buffer-types = <0x480>;

			virtual-addr-pool = <0x1000000 0x24800000>;

			qcom,secure-context-bank;

		};

	};

};

arch/arm64/boot/dts/qcom/sdm855.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -2294,3 +2294,4 @@ 
#include "sdm855-npu.dtsi"

#include "sdm855-pm.dtsi"

#include "sdm855-audio.dtsi"

#include "sdm855-vidc.dtsi"

drivers/media/platform/msm/vidc/msm_vidc_platform.c

+82 −1
Original line number Diff line number Diff line 
/* Copyright (c) 2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -50,6 +50,19 @@ static struct msm_vidc_codec_data default_codec_data[] = { 
	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 125, 675, 320),

};



/* Update with 855 data */

static struct msm_vidc_codec_data sdm855_codec_data[] =  {

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_ENCODER, 10, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_TME, MSM_VIDC_ENCODER, 0, 540, 540),

	CODEC_ENTRY(V4L2_PIX_FMT_MPEG2, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_VP8, MSM_VIDC_DECODER, 10, 200, 200),

	CODEC_ENTRY(V4L2_PIX_FMT_VP9, MSM_VIDC_DECODER, 10, 200, 200),

};



static struct msm_vidc_codec_data sdm845_codec_data[] =  {

	CODEC_ENTRY(V4L2_PIX_FMT_H264, MSM_VIDC_ENCODER, 125, 675, 320),

	CODEC_ENTRY(V4L2_PIX_FMT_HEVC, MSM_VIDC_ENCODER, 125, 675, 320),
@@ -101,6 +114,57 @@ static struct msm_vidc_common_data default_common_data[] = { 
	},

};



static struct msm_vidc_common_data sdm855_common_data[] = {

	{

		.key = "qcom,never-unload-fw",

		.value = 1,

	},

	{

		.key = "qcom,sw-power-collapse",

		.value = 1,

	},

	{

		.key = "qcom,domain-attr-non-fatal-faults",

		.value = 1,

	},

	{

		.key = "qcom,max-secure-instances",

		.value = 5,

	},

	{

		.key = "qcom,max-hw-load",

		.value = 4147200,	/* 4096x2160@120 */

	},

	{

		.key = "qcom,max-hq-mbs-per-frame",

		.value = 8160,

	},

	{

		.key = "qcom,max-hq-frames-per-sec",

		.value = 60,

	},

	{

		.key = "qcom,max-b-frame-size",

		.value = 8160,

	},

	{

		.key = "qcom,max-b-frames-per-sec",

		.value = 60,

	},

	{

		.key = "qcom,power-collapse-delay",

		.value = 1500,

	},

	{

		.key = "qcom,hw-resp-timeout",

		.value = 1000,

	},

	{

		.key = "qcom,debug-timeout",

		.value = 0,

	},

};



static struct msm_vidc_common_data sdm845_common_data[] = {

	{

		.key = "qcom,never-unload-fw",
@@ -255,6 +319,19 @@ static struct msm_vidc_platform_data default_data = { 
	.sku_version = 0,

};



static struct msm_vidc_platform_data sdm855_data = {

	.codec_data = sdm855_codec_data,

	.codec_data_length =  ARRAY_SIZE(sdm855_codec_data),

	.common_data = sdm855_common_data,

	.common_data_length =  ARRAY_SIZE(sdm855_common_data),

	.csc_data.vpe_csc_custom_bias_coeff = vpe_csc_custom_bias_coeff,

	.csc_data.vpe_csc_custom_matrix_coeff = vpe_csc_custom_matrix_coeff,

	.csc_data.vpe_csc_custom_limit_coeff = vpe_csc_custom_limit_coeff,

	.efuse_data = NULL,

	.efuse_data_length = 0,

	.sku_version = 0,

};



static struct msm_vidc_platform_data sdm845_data = {

	.codec_data = sdm845_codec_data,

	.codec_data_length =  ARRAY_SIZE(sdm845_codec_data),
@@ -282,6 +359,10 @@ static struct msm_vidc_platform_data sdm670_data = { 
};



static const struct of_device_id msm_vidc_dt_match[] = {

	{

		.compatible = "qcom,sdm855-vidc",

		.data = &sdm855_data,

	},

	{

		.compatible = "qcom,sdm845-vidc",

		.data = &sdm845_data,

drivers/media/platform/msm/vidc/venus_boot.c

+18 −39
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -35,25 +35,16 @@ 
#include "venus_boot.h"



/* VENUS WRAPPER registers */

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v1 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1018)

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v1 \

				(VIDC_WRAPPER_BASE_OFFS + 0x101C)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v1 \

#define VENUS_WRAPPER_SEC_CPA_START_ADDR			\

				(VIDC_WRAPPER_BASE_OFFS + 0x1020)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v1 \

#define VENUS_WRAPPER_SEC_CPA_END_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x1024)



#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v2 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1020)

#define VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v2 \

				(VIDC_WRAPPER_BASE_OFFS + 0x1024)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v2 \

#define VENUS_WRAPPER_SEC_FW_START_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x1028)

#define VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v2 \

#define VENUS_WRAPPER_SEC_FW_END_ADDR				\

				(VIDC_WRAPPER_BASE_OFFS + 0x102C)



#define VENUS_WRAPPER_SW_RESET	(VIDC_WRAPPER_BASE_OFFS + 0x3000)

#define VENUS_WRAPPER_A9SS_SW_RESET	(VIDC_WRAPPER_BASE_OFFS + 0x3000)



/* VENUS VBIF registers */

#define VENUS_VBIF_CLKON_FORCE_ON			BIT(0)
@@ -210,27 +201,15 @@ static int pil_venus_auth_and_reset(void) 


	if (iommu_present) {

		u32 cpa_start_addr, cpa_end_addr, fw_start_addr, fw_end_addr;

		/* Get the cpa and fw start/end addr based on Venus version */

		if (venus_data->hw_ver_major == 0x1 &&

				venus_data->hw_ver_minor <= 1) {

			cpa_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v1;

			cpa_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v1;

			fw_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v1;

			fw_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v1;

		} else {

		/* Get the cpa and fw start/end addr */

		cpa_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_START_ADDR_v2;

			VENUS_WRAPPER_SEC_CPA_START_ADDR;

		cpa_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_CPA_END_ADDR_v2;

			VENUS_WRAPPER_SEC_CPA_END_ADDR;

		fw_start_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_START_ADDR_v2;

			VENUS_WRAPPER_SEC_FW_START_ADDR;

		fw_end_addr =

				VENUS_WRAPPER_VBIF_SS_SEC_FW_END_ADDR_v2;

		}

			VENUS_WRAPPER_SEC_FW_END_ADDR;



		/* Program CPA start and end address */

		writel_relaxed(0, reg_base + cpa_start_addr);
@@ -303,7 +282,7 @@ static int pil_venus_auth_and_reset(void) 
		}

	}

	/* Bring Arm9 out of reset */

	writel_relaxed(0, reg_base + VENUS_WRAPPER_SW_RESET);

	writel_relaxed(0, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);



	venus_data->is_booted = 1;

	return 0;
@@ -328,9 +307,9 @@ static int pil_venus_shutdown(void) 
		return 0;



	/* Assert the reset to ARM9 */

	reg = readl_relaxed(reg_base + VENUS_WRAPPER_SW_RESET);

	reg = readl_relaxed(reg_base + VENUS_WRAPPER_A9SS_SW_RESET);

	reg |= BIT(4);

	writel_relaxed(reg, reg_base + VENUS_WRAPPER_SW_RESET);

	writel_relaxed(reg, reg_base + VENUS_WRAPPER_A9SS_SW_RESET);



	/* Make sure reset is asserted before the mapping is removed */

	mb();